DE602004018951D1 - Verfahren zum Herstellen von zusammengesetzten Wafern - Google Patents
Verfahren zum Herstellen von zusammengesetzten WafernInfo
- Publication number
- DE602004018951D1 DE602004018951D1 DE602004018951T DE602004018951T DE602004018951D1 DE 602004018951 D1 DE602004018951 D1 DE 602004018951D1 DE 602004018951 T DE602004018951 T DE 602004018951T DE 602004018951 T DE602004018951 T DE 602004018951T DE 602004018951 D1 DE602004018951 D1 DE 602004018951D1
- Authority
- DE
- Germany
- Prior art keywords
- donor substrate
- substrate
- initial
- initial donor
- compound material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/93—Ternary or quaternary semiconductor comprised of elements from three different groups, e.g. I-III-V
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04292655A EP1667223B1 (de) | 2004-11-09 | 2004-11-09 | Verfahren zum Herstellen von zusammengesetzten Wafern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602004018951D1 true DE602004018951D1 (de) | 2009-02-26 |
Family
ID=34931512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602004018951T Active DE602004018951D1 (de) | 2004-11-09 | 2004-11-09 | Verfahren zum Herstellen von zusammengesetzten Wafern |
Country Status (9)
| Country | Link |
|---|---|
| US (3) | US7531428B2 (de) |
| EP (2) | EP1962340A3 (de) |
| JP (1) | JP4489671B2 (de) |
| KR (1) | KR100746182B1 (de) |
| CN (2) | CN100426459C (de) |
| AT (1) | ATE420461T1 (de) |
| DE (1) | DE602004018951D1 (de) |
| SG (1) | SG122972A1 (de) |
| TW (2) | TWI303842B (de) |
Families Citing this family (78)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
| US20070023761A1 (en) * | 2005-07-26 | 2007-02-01 | Robbins Virginia M | Silicon carbon germanium (SiCGe) substrate for a group III nitride-based device |
| JP5003033B2 (ja) * | 2006-06-30 | 2012-08-15 | 住友電気工業株式会社 | ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法 |
| JP4873467B2 (ja) * | 2006-07-27 | 2012-02-08 | 独立行政法人産業技術総合研究所 | オフ角を有する単結晶基板の製造方法 |
| JP5016321B2 (ja) * | 2007-02-22 | 2012-09-05 | 東京応化工業株式会社 | サポートプレートの処理方法 |
| WO2008134828A2 (en) * | 2007-05-04 | 2008-11-13 | Katholieke Universiteit Leuven | Tissue degeneration protection |
| JP5143477B2 (ja) * | 2007-05-31 | 2013-02-13 | 信越化学工業株式会社 | Ｓｏｉウエーハの製造方法 |
| US20090061593A1 (en) * | 2007-08-28 | 2009-03-05 | Kishor Purushottam Gadkaree | Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment |
| US20120167819A1 (en) * | 2007-10-06 | 2012-07-05 | Solexel, Inc. | Method for reconstructing a semiconductor template |
| JP5522917B2 (ja) | 2007-10-10 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Ｓｏｉ基板の製造方法 |
| WO2009057669A1 (en) * | 2007-11-01 | 2009-05-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing photoelectric conversion device |
| WO2009063288A1 (en) * | 2007-11-15 | 2009-05-22 | S.O.I.Tec Silicon On Insulator Technologies | Semiconductor structure having a protective layer |
| JP5297219B2 (ja) * | 2008-02-29 | 2013-09-25 | 信越化学工業株式会社 | 単結晶薄膜を有する基板の製造方法 |
| CN101521155B (zh) * | 2008-02-29 | 2012-09-12 | 信越化学工业株式会社 | 制备具有单晶薄膜的基板的方法 |
| FR2928775B1 (fr) * | 2008-03-11 | 2011-12-09 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semiconducteur sur isolant |
| WO2009141724A1 (en) * | 2008-05-23 | 2009-11-26 | S.O.I.Tec Silicon On Insulator Technologies | Formation of substantially pit free indium gallium nitride |
| EP2329056B1 (de) | 2008-08-28 | 2012-12-19 | Soitec | Auf uv basierende überwachung und regelung von chlorid in einem gasstrom |
| US8679942B2 (en) * | 2008-11-26 | 2014-03-25 | Soitec | Strain engineered composite semiconductor substrates and methods of forming same |
| US8278167B2 (en) * | 2008-12-18 | 2012-10-02 | Micron Technology, Inc. | Method and structure for integrating capacitor-less memory cell with logic |
| JP2010165927A (ja) * | 2009-01-16 | 2010-07-29 | Sumitomo Electric Ind Ltd | 発光素子用基板 |
| US8198172B2 (en) * | 2009-02-25 | 2012-06-12 | Micron Technology, Inc. | Methods of forming integrated circuits using donor and acceptor substrates |
| US8178396B2 (en) | 2009-03-11 | 2012-05-15 | Micron Technology, Inc. | Methods for forming three-dimensional memory devices, and related structures |
| JP2010232609A (ja) * | 2009-03-30 | 2010-10-14 | Hitachi Cable Ltd | Ｉｉｉ族窒化物半導体複合基板、ｉｉｉ族窒化物半導体基板、及びｉｉｉ族窒化物半導体複合基板の製造方法 |
| US8871109B2 (en) * | 2009-04-28 | 2014-10-28 | Gtat Corporation | Method for preparing a donor surface for reuse |
| WO2010127320A2 (en) * | 2009-04-30 | 2010-11-04 | Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University | Methods for wafer bonding, and for nucleating bonding nanophases |
| WO2010150671A1 (en) * | 2009-06-24 | 2010-12-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate and method for manufacturing soi substrate |
| US8278187B2 (en) * | 2009-06-24 | 2012-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments |
| SG178061A1 (en) * | 2009-08-25 | 2012-03-29 | Semiconductor Energy Lab | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate |
| US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
| JP2011077102A (ja) * | 2009-09-29 | 2011-04-14 | Toyoda Gosei Co Ltd | ウエハ、ｉｉｉ族窒化物系化合物半導体素子、及びそれらの製造方法 |
| WO2011043178A1 (en) * | 2009-10-09 | 2011-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate |
| US8461566B2 (en) | 2009-11-02 | 2013-06-11 | Micron Technology, Inc. | Methods, structures and devices for increasing memory density |
| US8921239B2 (en) * | 2009-12-15 | 2014-12-30 | Soitec | Process for recycling a substrate |
| US9012253B2 (en) * | 2009-12-16 | 2015-04-21 | Micron Technology, Inc. | Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods |
| WO2011084381A2 (en) * | 2009-12-21 | 2011-07-14 | Applied Materials, Inc. | Cleaning optimization of pecvd solar films |
| US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
| US8507966B2 (en) | 2010-03-02 | 2013-08-13 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
| US8513722B2 (en) * | 2010-03-02 | 2013-08-20 | Micron Technology, Inc. | Floating body cell structures, devices including same, and methods for forming same |
| US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
| US8288795B2 (en) * | 2010-03-02 | 2012-10-16 | Micron Technology, Inc. | Thyristor based memory cells, devices and systems including the same and methods for forming the same |
| US8609453B2 (en) * | 2010-11-22 | 2013-12-17 | International Business Machines Corporation | Low cost solar cell manufacture method employing a reusable substrate |
| US9082948B2 (en) | 2011-02-03 | 2015-07-14 | Soitec | Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods |
| US9142412B2 (en) | 2011-02-03 | 2015-09-22 | Soitec | Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods |
| US8436363B2 (en) | 2011-02-03 | 2013-05-07 | Soitec | Metallic carrier for layer transfer and methods for forming the same |
| FR2971365B1 (fr) * | 2011-02-08 | 2013-02-22 | Soitec Silicon On Insulator | Méthode de recyclage d'un substrat source |
| US8598621B2 (en) | 2011-02-11 | 2013-12-03 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
| US8952418B2 (en) | 2011-03-01 | 2015-02-10 | Micron Technology, Inc. | Gated bipolar junction transistors |
| US8519431B2 (en) | 2011-03-08 | 2013-08-27 | Micron Technology, Inc. | Thyristors |
| US20130137244A1 (en) * | 2011-05-26 | 2013-05-30 | Solexel, Inc. | Method and apparatus for reconditioning a carrier wafer for reuse |
| US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
| US8772848B2 (en) | 2011-07-26 | 2014-07-08 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
| JP5587848B2 (ja) * | 2011-10-11 | 2014-09-10 | 日本電信電話株式会社 | 半導体積層構造の製造方法 |
| US9589801B2 (en) | 2011-10-31 | 2017-03-07 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization |
| KR20130049484A (ko) * | 2011-11-04 | 2013-05-14 | 삼성코닝정밀소재 주식회사 | 박막 접합 기판 제조방법 |
| WO2013093590A1 (en) | 2011-12-23 | 2013-06-27 | Soitec | Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods |
| US8916954B2 (en) | 2012-02-05 | 2014-12-23 | Gtat Corporation | Multi-layer metal support |
| US8841161B2 (en) | 2012-02-05 | 2014-09-23 | GTAT.Corporation | Method for forming flexible solar cells |
| JP5285793B2 (ja) * | 2012-05-10 | 2013-09-11 | 東京応化工業株式会社 | サポートプレートの処理方法 |
| JP2013247362A (ja) * | 2012-05-29 | 2013-12-09 | Samsung Corning Precision Materials Co Ltd | 半導体素子用薄膜貼り合わせ基板の製造方法 |
| JP2015528783A (ja) | 2012-06-29 | 2015-10-01 | コーニング インコーポレイテッド | 半導体プロセスのためのガラス―セラミック基板 |
| US8785294B2 (en) | 2012-07-26 | 2014-07-22 | Gtat Corporation | Silicon carbide lamina |
| US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
| WO2014052476A2 (en) | 2012-09-25 | 2014-04-03 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On... | Methods for wafer bonding, and for nucleating bonding nanophases |
| CN105051919A (zh) | 2013-01-16 | 2015-11-11 | Qmat股份有限公司 | 用于形成光电器件的技术 |
| US11721547B2 (en) * | 2013-03-14 | 2023-08-08 | Infineon Technologies Ag | Method for manufacturing a silicon carbide substrate for an electrical silicon carbide device, a silicon carbide substrate and an electrical silicon carbide device |
| JP5888286B2 (ja) | 2013-06-26 | 2016-03-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| FR3007892B1 (fr) * | 2013-06-27 | 2015-07-31 | Commissariat Energie Atomique | Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive |
| US9876081B2 (en) | 2013-07-16 | 2018-01-23 | The United States Of America, As Represented By The Secretary Of The Navy | Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates |
| JP6136786B2 (ja) | 2013-09-05 | 2017-05-31 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| US9761671B2 (en) | 2013-12-30 | 2017-09-12 | Veeco Instruments, Inc. | Engineered substrates for use in crystalline-nitride based devices |
| US10822718B2 (en) * | 2016-03-23 | 2020-11-03 | Tokuyama Corporation | Method for producing aluminum nitride single crystal substrate |
| US10679852B2 (en) * | 2016-06-13 | 2020-06-09 | QROMIS, Inc. | Multi-deposition process for high quality gallium nitride device manufacturing |
| US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
| US20180033609A1 (en) * | 2016-07-28 | 2018-02-01 | QMAT, Inc. | Removal of non-cleaved/non-transferred material from donor substrate |
| FR3055064B1 (fr) * | 2016-08-11 | 2018-10-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d'une couche epitaxiee sur une plaque de croissance |
| DE102018111450A1 (de) | 2018-05-14 | 2019-11-14 | Infineon Technologies Ag | Verfahren zum Verarbeiten eines Breiter-Bandabstand-Halbleiterwafers, Verfahren zum Bilden einer Mehrzahl von dünnen Breiter-Bandabstand-Halbleiterwafern und Breiter-Bandabstand-Halbleiterwafer |
| US11664357B2 (en) | 2018-07-03 | 2023-05-30 | Adeia Semiconductor Bonding Technologies Inc. | Techniques for joining dissimilar materials in microelectronics |
| US20210254241A1 (en) * | 2020-02-14 | 2021-08-19 | Kyocera Corporation | Method for recycling substrate, method for manufacturing semiconductor device, and semiconductor device |
Family Cites Families (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US38466A (en) * | 1863-05-12 | Improved medicine for piles | ||
| IT1210982B (it) * | 1981-02-03 | 1989-09-29 | Giuseppe Stefano Piana | Capsula a perdere, per la confezione di preparati idrosolubili in dosi, atti a consentire la preparazione di bevande calde in genere. |
| FI83197C (fi) * | 1984-10-23 | 1991-06-10 | Mars G B Ltd | Dryckpaose. |
| JPH05275332A (ja) * | 1992-03-26 | 1993-10-22 | Shimadzu Corp | ヘテロエピタキシャル膜の製膜方法 |
| US20030087503A1 (en) | 1994-03-10 | 2003-05-08 | Canon Kabushiki Kaisha | Process for production of semiconductor substrate |
| JP3352340B2 (ja) * | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | 半導体基体とその製造方法 |
| DE69739368D1 (de) * | 1996-08-27 | 2009-05-28 | Seiko Epson Corp | Trennverfahren und Verfahren zur Übertragung eines Dünnfilmbauelements |
| USRE38466E1 (en) | 1996-11-12 | 2004-03-16 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
| US6127199A (en) * | 1996-11-12 | 2000-10-03 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
| EP0874405A3 (de) * | 1997-03-25 | 2004-09-15 | Mitsubishi Cable Industries, Ltd. | Element auf Basis von GaN mit niedriger Versetzungsdichte, seine Verwendung und Herstellungsverfahren |
| JP3492142B2 (ja) * | 1997-03-27 | 2004-02-03 | キヤノン株式会社 | 半導体基材の製造方法 |
| US6251754B1 (en) * | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
| JPH10335617A (ja) * | 1997-05-30 | 1998-12-18 | Denso Corp | 半導体基板の製造方法 |
| JPH1174209A (ja) * | 1997-08-27 | 1999-03-16 | Denso Corp | 半導体基板の製造方法 |
| FR2774214B1 (fr) | 1998-01-28 | 2002-02-08 | Commissariat Energie Atomique | PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI |
| JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ |
| US6328796B1 (en) | 1999-02-01 | 2001-12-11 | The United States Of America As Represented By The Secretary Of The Navy | Single-crystal material on non-single-crystalline substrate |
| JP4313874B2 (ja) * | 1999-02-02 | 2009-08-12 | キヤノン株式会社 | 基板の製造方法 |
| US6468923B1 (en) * | 1999-03-26 | 2002-10-22 | Canon Kabushiki Kaisha | Method of producing semiconductor member |
| JP3453544B2 (ja) * | 1999-03-26 | 2003-10-06 | キヤノン株式会社 | 半導体部材の作製方法 |
| WO2001006564A1 (en) * | 1999-07-15 | 2001-01-25 | Shin-Etsu Handotai Co., Ltd. | Method for producing bonded wafer and bonded wafer |
| US6500732B1 (en) | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
| US6223650B1 (en) * | 1999-09-30 | 2001-05-01 | Robert M. Stuck | Apparatus for conveyorized toasting of breads and like food items |
| JP3943782B2 (ja) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
| US6475882B1 (en) * | 1999-12-20 | 2002-11-05 | Nitride Semiconductors Co., Ltd. | Method for producing GaN-based compound semiconductor and GaN-based compound semiconductor device |
| EP1277240B1 (de) | 2000-04-26 | 2015-05-20 | OSRAM Opto Semiconductors GmbH | Verfahren zur Herstellung eines lichtmittierenden Halbleiterbauelements |
| FR2817395B1 (fr) | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
| FR2817394B1 (fr) | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
| US6740345B2 (en) * | 2000-12-22 | 2004-05-25 | Edward Zhihua Cai | Beverage making cartridge |
| US6497763B2 (en) | 2001-01-19 | 2002-12-24 | The United States Of America As Represented By The Secretary Of The Navy | Electronic device with composite substrate |
| JP3826825B2 (ja) * | 2001-04-12 | 2006-09-27 | 住友電気工業株式会社 | 窒化ガリウム結晶への酸素ドーピング方法と酸素ドープされたｎ型窒化ガリウム単結晶基板 |
| JP2003022989A (ja) * | 2001-07-09 | 2003-01-24 | Sumitomo Mitsubishi Silicon Corp | エピタキシャル半導体ウェーハ及びその製造方法 |
| FR2828762B1 (fr) | 2001-08-14 | 2003-12-05 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique |
| JP2003101025A (ja) * | 2001-09-26 | 2003-04-04 | Toshiba Corp | 半導体装置 |
| FR2834124B1 (fr) | 2001-12-20 | 2005-05-20 | Osram Opto Semiconductors Gmbh | Procede de production de couches semi-conductrices |
| FR2834123B1 (fr) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report |
| JP2003204048A (ja) | 2002-01-09 | 2003-07-18 | Shin Etsu Handotai Co Ltd | Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ |
| WO2004007816A1 (en) * | 2002-07-17 | 2004-01-22 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating substrates, in particular for optics, electronics or optoelectronics________________________________________ |
| US7008857B2 (en) * | 2002-08-26 | 2006-03-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom |
| CN100557785C (zh) * | 2002-08-26 | 2009-11-04 | S.O.I.Tec绝缘体上硅技术公司 | 具有缓冲结构的晶片的再循环 |
| WO2004019404A2 (en) * | 2002-08-26 | 2004-03-04 | S.O.I.Tec Silicon On Insulator Technologies | Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom |
| JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
| US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
-
2004
- 2004-11-09 EP EP08007333A patent/EP1962340A3/de not_active Withdrawn
- 2004-11-09 DE DE602004018951T patent/DE602004018951D1/de active Active
- 2004-11-09 AT AT04292655T patent/ATE420461T1/de not_active IP Right Cessation
- 2004-11-09 EP EP04292655A patent/EP1667223B1/de active Active
-
2005
- 2005-03-18 US US11/084,553 patent/US7531428B2/en active Active
- 2005-08-31 TW TW094129941A patent/TWI303842B/zh active
- 2005-08-31 TW TW096148068A patent/TWI367544B/zh active
- 2005-09-16 JP JP2005270897A patent/JP4489671B2/ja active Active
- 2005-11-03 KR KR1020050104993A patent/KR100746182B1/ko active IP Right Grant
- 2005-11-08 CN CNB2005101156304A patent/CN100426459C/zh active Active
- 2005-11-08 SG SG200508509A patent/SG122972A1/en unknown
- 2005-11-08 CN CN200810002207.7A patent/CN101221895B/zh active Active
-
2009
- 2009-03-31 US US12/415,085 patent/US7851330B2/en active Active
-
2010
- 2010-11-04 US US12/939,590 patent/US7968909B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW200616014A (en) | 2006-05-16 |
| KR20060052446A (ko) | 2006-05-19 |
| JP4489671B2 (ja) | 2010-06-23 |
| TWI367544B (en) | 2012-07-01 |
| EP1962340A3 (de) | 2009-12-23 |
| JP2006140445A (ja) | 2006-06-01 |
| SG122972A1 (en) | 2006-06-29 |
| EP1962340A2 (de) | 2008-08-27 |
| US20060099776A1 (en) | 2006-05-11 |
| CN101221895A (zh) | 2008-07-16 |
| US7851330B2 (en) | 2010-12-14 |
| CN100426459C (zh) | 2008-10-15 |
| EP1667223A1 (de) | 2006-06-07 |
| TWI303842B (en) | 2008-12-01 |
| KR100746182B1 (ko) | 2007-08-03 |
| US20090191719A1 (en) | 2009-07-30 |
| US7968909B2 (en) | 2011-06-28 |
| US7531428B2 (en) | 2009-05-12 |
| EP1667223B1 (de) | 2009-01-07 |
| ATE420461T1 (de) | 2009-01-15 |
| CN1790620A (zh) | 2006-06-21 |
| US20110049528A1 (en) | 2011-03-03 |
| CN101221895B (zh) | 2014-04-23 |
| TW200824037A (en) | 2008-06-01 |
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