DE602005015225D1 - Speicherbefehlsverzögerungsausgleich in einer verketteten speichertopologie - Google Patents
Speicherbefehlsverzögerungsausgleich in einer verketteten speichertopologieInfo
- Publication number
- DE602005015225D1 DE602005015225D1 DE602005015225T DE602005015225T DE602005015225D1 DE 602005015225 D1 DE602005015225 D1 DE 602005015225D1 DE 602005015225 T DE602005015225 T DE 602005015225T DE 602005015225 T DE602005015225 T DE 602005015225T DE 602005015225 D1 DE602005015225 D1 DE 602005015225D1
- Authority
- DE
- Germany
- Prior art keywords
- memory
- memory devices
- communication delay
- chained
- topology
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/922,299 US7669027B2 (en) | 2004-08-19 | 2004-08-19 | Memory command delay balancing in a daisy-chained memory topology |
PCT/US2005/028535 WO2006023360A1 (en) | 2004-08-19 | 2005-08-09 | Memory command delay balancing in a daisy-chained memory topology |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005015225D1 true DE602005015225D1 (de) | 2009-08-13 |
Family
ID=35311582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005015225T Active DE602005015225D1 (de) | 2004-08-19 | 2005-08-09 | Speicherbefehlsverzögerungsausgleich in einer verketteten speichertopologie |
Country Status (9)
Country | Link |
---|---|
US (5) | US7669027B2 (de) |
EP (1) | EP1779251B1 (de) |
JP (1) | JP4742347B2 (de) |
KR (1) | KR100883007B1 (de) |
CN (1) | CN101014941B (de) |
AT (1) | ATE435457T1 (de) |
DE (1) | DE602005015225D1 (de) |
TW (1) | TWI317068B (de) |
WO (1) | WO2006023360A1 (de) |
Families Citing this family (79)
Publication number | Priority date | Publication date | Assignee | Title |
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US7669027B2 (en) * | 2004-08-19 | 2010-02-23 | Micron Technology, Inc. | Memory command delay balancing in a daisy-chained memory topology |
KR100666225B1 (ko) * | 2005-02-17 | 2007-01-09 | 삼성전자주식회사 | 데이지 체인을 형성하는 멀티 디바이스 시스템 및 이의 구동방법 |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8041881B2 (en) * | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8244971B2 (en) * | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US7580312B2 (en) * | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8089795B2 (en) * | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US7472220B2 (en) * | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US7386656B2 (en) * | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US9542352B2 (en) * | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US20080126690A1 (en) * | 2006-02-09 | 2008-05-29 | Rajan Suresh N | Memory module with memory stack |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
WO2007002324A2 (en) * | 2005-06-24 | 2007-01-04 | Metaram, Inc. | An integrated memory core and memory interface circuit |
US8090897B2 (en) * | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
GB2444663B (en) | 2005-09-02 | 2011-12-07 | Metaram Inc | Methods and apparatus of stacking drams |
US20070165457A1 (en) * | 2005-09-30 | 2007-07-19 | Jin-Ki Kim | Nonvolatile memory system |
US20070076502A1 (en) * | 2005-09-30 | 2007-04-05 | Pyeon Hong B | Daisy chain cascading devices |
US7652922B2 (en) | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
TWI543185B (zh) | 2005-09-30 | 2016-07-21 | 考文森智財管理公司 | 具有輸出控制之記憶體及其系統 |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
DE102006062725B4 (de) * | 2006-04-15 | 2018-01-18 | Polaris Innovations Ltd. | Speichersystem mit integrierten Speicherbausteinen sowie Verfahren zum Betrieb eines Speichersystems |
JP5065618B2 (ja) * | 2006-05-16 | 2012-11-07 | 株式会社日立製作所 | メモリモジュール |
US7546410B2 (en) * | 2006-07-26 | 2009-06-09 | International Business Machines Corporation | Self timed memory chip having an apportionable data bus |
US7660942B2 (en) * | 2006-07-26 | 2010-02-09 | International Business Machines Corporation | Daisy chainable self timed memory chip |
US7577811B2 (en) * | 2006-07-26 | 2009-08-18 | International Business Machines Corporation | Memory controller for daisy chained self timed memory chips |
US7660940B2 (en) * | 2006-07-26 | 2010-02-09 | International Business Machines Corporation | Carrier having daisy chain of self timed memory chips |
US7545664B2 (en) * | 2006-07-26 | 2009-06-09 | International Business Machines Corporation | Memory system having self timed daisy chained memory chips |
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US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
US8209479B2 (en) * | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
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EP2441007A1 (de) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programmierung von dimm-abschlusswiderstandswerten |
US8094507B2 (en) | 2009-07-09 | 2012-01-10 | Micron Technology, Inc. | Command latency systems and methods |
US8742814B2 (en) | 2009-07-15 | 2014-06-03 | Yehuda Binder | Sequentially operated modules |
US8602833B2 (en) * | 2009-08-06 | 2013-12-10 | May Patents Ltd. | Puzzle with conductive path |
US8245024B2 (en) | 2009-08-21 | 2012-08-14 | Micron Technology, Inc. | Booting in systems having devices coupled in a chained configuration |
US8966208B2 (en) * | 2010-02-25 | 2015-02-24 | Conversant Ip Management Inc. | Semiconductor memory device with plural memory die and controller die |
US9401225B2 (en) | 2010-11-19 | 2016-07-26 | Rambus Inc. | Timing-drift calibration |
US9597607B2 (en) | 2011-08-26 | 2017-03-21 | Littlebits Electronics Inc. | Modular electronic building systems with magnetic interconnections and methods of using the same |
US9019718B2 (en) | 2011-08-26 | 2015-04-28 | Littlebits Electronics Inc. | Modular electronic building systems with magnetic interconnections and methods of using the same |
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CN102736996A (zh) * | 2011-12-27 | 2012-10-17 | 华为技术有限公司 | 一种减少存储控制器接口占用的方法及高速存储器 |
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CN104360977B (zh) * | 2014-12-10 | 2018-02-06 | 浪潮(北京)电子信息产业有限公司 | 一种管理高速串行传输接口的方法及系统 |
US10261697B2 (en) | 2015-06-08 | 2019-04-16 | Samsung Electronics Co., Ltd. | Storage device and operating method of storage device |
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EP3511837B1 (de) | 2016-09-29 | 2023-01-18 | Huawei Technologies Co., Ltd. | Chip mit erweiterbarem speicher |
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KR20180127710A (ko) | 2017-05-22 | 2018-11-30 | 에스케이하이닉스 주식회사 | 메모리 모듈 및 이를 포함하는 메모리 시스템 |
CN108256209A (zh) * | 2018-01-15 | 2018-07-06 | 郑州云海信息技术有限公司 | 一种菊花链布线时钟信号传输路径电路 |
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KR20210145480A (ko) | 2020-05-25 | 2021-12-02 | 삼성전자주식회사 | 디스플레이 구동 장치 및 디스플레이 구동 장치를 포함하는 디스플레이 장치 |
CN114141279A (zh) | 2020-09-04 | 2022-03-04 | 美光科技公司 | 存储器拓扑 |
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-
2004
- 2004-08-19 US US10/922,299 patent/US7669027B2/en not_active Expired - Fee Related
-
2005
- 2005-08-09 AT AT05784488T patent/ATE435457T1/de not_active IP Right Cessation
- 2005-08-09 CN CN2005800283599A patent/CN101014941B/zh not_active Expired - Fee Related
- 2005-08-09 JP JP2007527878A patent/JP4742347B2/ja not_active Expired - Fee Related
- 2005-08-09 KR KR1020077002577A patent/KR100883007B1/ko not_active IP Right Cessation
- 2005-08-09 DE DE602005015225T patent/DE602005015225D1/de active Active
- 2005-08-09 WO PCT/US2005/028535 patent/WO2006023360A1/en active Application Filing
- 2005-08-09 EP EP05784488A patent/EP1779251B1/de not_active Not-in-force
- 2005-08-12 TW TW094127497A patent/TWI317068B/zh not_active IP Right Cessation
-
2010
- 2010-01-19 US US12/689,495 patent/US7908451B2/en not_active Expired - Fee Related
-
2011
- 2011-02-23 US US13/033,364 patent/US8166268B2/en not_active Expired - Fee Related
-
2012
- 2012-04-23 US US13/453,132 patent/US8612712B2/en not_active Expired - Fee Related
-
2013
- 2013-12-02 US US14/093,940 patent/US8935505B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008510257A (ja) | 2008-04-03 |
KR100883007B1 (ko) | 2009-02-12 |
ATE435457T1 (de) | 2009-07-15 |
US8612712B2 (en) | 2013-12-17 |
EP1779251A1 (de) | 2007-05-02 |
CN101014941A (zh) | 2007-08-08 |
TWI317068B (en) | 2009-11-11 |
US20120210089A1 (en) | 2012-08-16 |
JP4742347B2 (ja) | 2011-08-10 |
CN101014941B (zh) | 2013-03-06 |
WO2006023360A1 (en) | 2006-03-02 |
US20100122059A1 (en) | 2010-05-13 |
US8166268B2 (en) | 2012-04-24 |
KR20070039117A (ko) | 2007-04-11 |
US20060041730A1 (en) | 2006-02-23 |
EP1779251B1 (de) | 2009-07-01 |
US20110145522A1 (en) | 2011-06-16 |
TW200619950A (en) | 2006-06-16 |
US8935505B2 (en) | 2015-01-13 |
US7908451B2 (en) | 2011-03-15 |
US20140089620A1 (en) | 2014-03-27 |
US7669027B2 (en) | 2010-02-23 |
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