DE602006013627D1 - Spekulative mikro-tiling-returns eines speichers - Google Patents

Spekulative mikro-tiling-returns eines speichers

Info

Publication number
DE602006013627D1
DE602006013627D1 DE602006013627T DE602006013627T DE602006013627D1 DE 602006013627 D1 DE602006013627 D1 DE 602006013627D1 DE 602006013627 T DE602006013627 T DE 602006013627T DE 602006013627 T DE602006013627 T DE 602006013627T DE 602006013627 D1 DE602006013627 D1 DE 602006013627D1
Authority
DE
Germany
Prior art keywords
memory
request
tiling
returns
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006013627T
Other languages
English (en)
Inventor
James Akiyama
William Clifford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE602006013627D1 publication Critical patent/DE602006013627D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
DE602006013627T 2005-06-23 2006-06-23 Spekulative mikro-tiling-returns eines speichers Active DE602006013627D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/165,390 US7587521B2 (en) 2005-06-23 2005-06-23 Mechanism for assembling memory access requests while speculatively returning data
PCT/US2006/024546 WO2007002445A2 (en) 2005-06-23 2006-06-23 Memory micro-tiling speculative returns

Publications (1)

Publication Number Publication Date
DE602006013627D1 true DE602006013627D1 (de) 2010-05-27

Family

ID=37545366

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006013627T Active DE602006013627D1 (de) 2005-06-23 2006-06-23 Spekulative mikro-tiling-returns eines speichers

Country Status (9)

Country Link
US (1) US7587521B2 (de)
EP (1) EP1894112B1 (de)
JP (1) JP4879981B2 (de)
KR (1) KR100958264B1 (de)
CN (1) CN101208672B (de)
AT (1) ATE464605T1 (de)
DE (1) DE602006013627D1 (de)
TW (1) TWI328169B (de)
WO (1) WO2007002445A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765366B2 (en) * 2005-06-23 2010-07-27 Intel Corporation Memory micro-tiling
US8332598B2 (en) * 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering
US8253751B2 (en) 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US7558941B2 (en) * 2005-06-30 2009-07-07 Intel Corporation Automatic detection of micro-tile enabled memory
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
SE531148C2 (sv) 2007-05-16 2009-01-07 Dinair Dev Ab Användning av ett material såsom filtergrundmaterial förfarande för tillverkning av filtergrundmaterial, filtergrundmaterial och filter
US8006032B2 (en) * 2007-08-22 2011-08-23 Globalfoundries Inc. Optimal solution to control data channels
JP2010027032A (ja) * 2008-06-17 2010-02-04 Nec Electronics Corp Ｆｉｆｏ装置及びｆｉｆｏバッファへのデータ格納方法
US20100058016A1 (en) * 2008-08-26 2010-03-04 Jari Nikara Method, apparatus and software product for multi-channel memory sandbox
US8359421B2 (en) * 2009-08-06 2013-01-22 Qualcomm Incorporated Partitioning a crossbar interconnect in a multi-channel memory system
US8880819B2 (en) 2011-12-13 2014-11-04 Micron Technology, Inc. Memory apparatuses, computer systems and methods for ordering memory responses
US10324768B2 (en) * 2014-12-17 2019-06-18 Intel Corporation Lightweight restricted transactional memory for speculative compiler optimization
GB2551351B (en) * 2016-06-14 2019-05-08 Imagination Tech Ltd Executing memory requests out of order
EP3270295A1 (de) * 2016-07-15 2018-01-17 Advanced Micro Devices, Inc. Speichersteuergerät mit virtuellem steuergerätemodus
US10037150B2 (en) 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US193293A (en) * 1877-07-17 Improvement in safe and vault
US179598A (en) * 1876-07-04 Improvement in cutter-heads
US3323109A (en) 1963-12-30 1967-05-30 North American Aviation Inc Multiple computer-multiple memory system
JPS51127626A (en) 1975-04-30 1976-11-06 Hitachi Ltd Information processor
US3988717A (en) 1975-08-06 1976-10-26 Litton Systems, Inc. General purpose computer or logic chip and system
NL7510904A (nl) 1975-09-17 1977-03-21 Philips Nv Woordgroepsprioriteitsinrichting.
US4124891A (en) 1976-11-18 1978-11-07 Honeywell Information Systems Inc. Memory access system
US4495570A (en) 1981-01-14 1985-01-22 Hitachi, Ltd. Processing request allocator for assignment of loads in a distributed processing system
US4504902A (en) 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
JPH0267622A (ja) 1988-09-01 1990-03-07 Kansai Nippon Denki Software Kk ディスク入出力方式
US5325510A (en) 1990-05-25 1994-06-28 Texas Instruments Incorporated Multiprocessor system and architecture with a computation system for minimizing duplicate read requests
US5251310A (en) 1990-06-29 1993-10-05 Digital Equipment Corporation Method and apparatus for exchanging blocks of information between a cache memory and a main memory
US5526507A (en) 1992-01-06 1996-06-11 Hill; Andrew J. W. Computer memory array control for accessing different memory banks simullaneously
US5459842A (en) 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
JPH0695959A (ja) * 1992-09-09 1994-04-08 Hitachi Ltd 情報処理装置
JP3240709B2 (ja) * 1992-10-30 2001-12-25 株式会社アドバンテスト メモリ試験装置
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5649157A (en) 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
WO1996041274A1 (en) * 1995-06-07 1996-12-19 Advanced Micro Devices, Inc. Dynamically reconfigurable data bus
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US6061773A (en) 1996-05-03 2000-05-09 Digital Equipment Corporation Virtual memory system with page table space separating a private space and a shared space in a virtual memory
US5761708A (en) 1996-05-31 1998-06-02 Sun Microsystems, Inc. Apparatus and method to speculatively initiate primary memory accesses
US5905725A (en) * 1996-12-16 1999-05-18 Juniper Networks High speed switching device
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US6308248B1 (en) 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
US5790118A (en) 1997-03-07 1998-08-04 International Business Machines Corporation Mobile client programmed to hide empty table elements
US5913231A (en) 1997-03-31 1999-06-15 International Business Machines Corporation Method and system for high speed memory address forwarding mechanism
US6145065A (en) 1997-05-02 2000-11-07 Matsushita Electric Industrial Co., Ltd. Memory access buffer and reordering apparatus using priorities
US6151641A (en) 1997-09-30 2000-11-21 Lsi Logic Corporation DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments
US6122709A (en) 1997-12-19 2000-09-19 Sun Microsystems, Inc. Cache with reduced tag information storage
WO1999034294A1 (en) 1997-12-24 1999-07-08 Creative Technology Ltd. Optimal multi-channel memory controller system
US6438675B1 (en) 1998-03-23 2002-08-20 Ati Technologies, Inc. Variable format memory access device
US6249851B1 (en) 1998-08-25 2001-06-19 Stmicroelectronics, Inc. Computer system having non-blocking cache and pipelined bus interface unit
US6453380B1 (en) 1999-01-23 2002-09-17 International Business Machines Corporation Address mapping for configurable memory system
US6389488B1 (en) 1999-01-28 2002-05-14 Advanced Micro Devices, Inc. Read ahead buffer for read accesses to system memory by input/output devices with buffer valid indication
US6708248B1 (en) 1999-07-23 2004-03-16 Rambus Inc. Memory system with channel multiplexing of multiple memory devices
JP2001060169A (ja) * 1999-08-24 2001-03-06 Hitachi Ltd キャッシュコントローラ及びコンピュータシステム
JP2001176282A (ja) 1999-12-20 2001-06-29 Fujitsu Ltd 半導体記憶装置およびその制御方法
US6678810B1 (en) 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US6430672B1 (en) 2000-07-17 2002-08-06 International Business Machines Corporation Method for performing address mapping using two lookup tables
EP1182564A3 (de) * 2000-08-21 2004-07-28 Texas Instruments France Lokaler Speicher mit Anzeigesbits zur Unterstützung von gleichzeitigem DMA- und CPU-Zugriff
US7006505B1 (en) * 2000-10-23 2006-02-28 Bay Microsystems, Inc. Memory management system and algorithm for network processor architecture
US6745272B2 (en) 2001-04-04 2004-06-01 Advanced Micro Devices, Inc. System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system
US7200759B2 (en) 2001-06-08 2007-04-03 Safenet B.V. Method and device for making information contents of a volatile semiconductor memory irretrievable
US20030056058A1 (en) 2001-09-17 2003-03-20 Alistair Veitch Logical volume data migration
US6812928B2 (en) 2002-01-30 2004-11-02 Sun Microsystems, Inc. Performance texture mapping by combining requests for image data
US20030179598A1 (en) 2002-03-20 2003-09-25 Yu-Guang Chen Device for selectively providing read-only data
US6842828B2 (en) 2002-04-30 2005-01-11 Intel Corporation Methods and arrangements to enhance an upbound path
US7028200B2 (en) 2002-05-15 2006-04-11 Broadcom Corporation Method and apparatus for adaptive power management of memory subsystem
US6934804B2 (en) 2002-05-28 2005-08-23 Sun Microsystems, Inc. Method and system for striping spares in a data storage system including an array of disk drives
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US6851030B2 (en) * 2002-10-16 2005-02-01 International Business Machines Corporation System and method for dynamically allocating associative resources
US7130229B2 (en) * 2002-11-08 2006-10-31 Intel Corporation Interleaved mirrored memory systems
US6836434B2 (en) 2002-11-21 2004-12-28 Micron Technology, Inc. Mode selection in a flash memory device
US7255895B2 (en) * 2003-01-21 2007-08-14 Bioarray Solutions, Ltd. Method for controlling solute loading of polymer microparticles
US7243172B2 (en) * 2003-10-14 2007-07-10 Broadcom Corporation Fragment storage for data alignment and merger
JP4601305B2 (ja) 2004-02-27 2010-12-22 富士通セミコンダクター株式会社 半導体装置
US8332598B2 (en) 2005-06-23 2012-12-11 Intel Corporation Memory micro-tiling request reordering

Also Published As

Publication number Publication date
KR100958264B1 (ko) 2010-05-19
TW200712886A (en) 2007-04-01
ATE464605T1 (de) 2010-04-15
US7587521B2 (en) 2009-09-08
JP4879981B2 (ja) 2012-02-22
JP2008544411A (ja) 2008-12-04
TWI328169B (en) 2010-08-01
KR20080014063A (ko) 2008-02-13
WO2007002445A2 (en) 2007-01-04
WO2007002445A3 (en) 2007-06-28
EP1894112A2 (de) 2008-03-05
CN101208672A (zh) 2008-06-25
US20060294264A1 (en) 2006-12-28
CN101208672B (zh) 2010-05-19
EP1894112B1 (de) 2010-04-14

Similar Documents

Publication Publication Date Title
ATE464605T1 (de) Spekulative mikro-tiling-returns eines speichers
TW200707454A (en) Memory micro-tiling
TW200710657A (en) Memory micro-tiling request reordering
GB2445294A (en) Method for proactive synchronization within a computer system
ATE474266T1 (de) Effiziente systemverwaltungssynchronisation und speicherzuteilung
AU2003232136A8 (en) Out of order dram sequencer
DE60308150D1 (de) Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem
NO20061380L (no) Fremgangsmate og anordning for tilordning av underbaemr i OFDMsystemer
BRPI0401685A (pt) Implementação de controle de acesso à memória utilizando otimizações
ATE509317T1 (de) Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung
TW200644539A (en) Specializing support for a federation relationship
ATE444529T1 (de) Buszugangs-arbitrierungsschema
TW200707190A (en) Partial page scheme for memory technologies
WO2007003370A3 (en) A memory arrangement for multi-processor systems
BRPI0510494B8 (pt) Dispositivo de armazenagem e aparelho hospedeiro
GB2456948A (en) Data file access control
GB2435780A (en) System,method and apparatus of securing an operating system
TW201714092A (en) Method for managing a memory apparatus, and associated memory apparatus thereof
TW200702992A (en) Methods and apparatus for dynamically managing banked memory
TW200735099A (en) Semiconductor memory, memory system, and operation method of semiconductor memory
TW200617674A (en) Direct processor cache access within a system having a coherent multi-processor protocol
WO2006012305A3 (en) Bank assignment for partitioned register banks
WO2010093661A3 (en) Microcontroller with special banking instructions
ATE458222T1 (de) Aufrechterhaltung der cachespeicherkoherenz zum direkten zugriff (dma), abschluss einer aufgabe, zur synchronisierung
TW200707202A (en) LPC configuration sharing method

Legal Events

Date Code Title Description
8364 No opposition during term of opposition