DE60202812D1 - Verwendung von Software-Unterbrechungsausnahmen in der Verwaltung von Übertragungen zwischen Prozessoren - Google Patents

Verwendung von Software-Unterbrechungsausnahmen in der Verwaltung von Übertragungen zwischen Prozessoren

Info

Publication number
DE60202812D1
DE60202812D1 DE60202812T DE60202812T DE60202812D1 DE 60202812 D1 DE60202812 D1 DE 60202812D1 DE 60202812 T DE60202812 T DE 60202812T DE 60202812 T DE60202812 T DE 60202812T DE 60202812 D1 DE60202812 D1 DE 60202812D1
Authority
DE
Germany
Prior art keywords
exceptions
transfers
processors
management
software interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60202812T
Other languages
English (en)
Other versions
DE60202812T2 (de
Inventor
Scott Paul Gary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE60202812D1 publication Critical patent/DE60202812D1/de
Application granted granted Critical
Publication of DE60202812T2 publication Critical patent/DE60202812T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/547—Remote procedure calls [RPC]; Web services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
DE60202812T 2001-06-08 2002-06-07 Verwendung von Software-Unterbrechungsausnahmen in der Verwaltung von Übertragungen zwischen Prozessoren Expired - Lifetime DE60202812T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/877,320 US20020178313A1 (en) 2001-03-30 2001-06-08 Using software interrupts to manage communication between data processors
US877320 2001-06-08

Publications (2)

Publication Number Publication Date
DE60202812D1 true DE60202812D1 (de) 2005-03-10
DE60202812T2 DE60202812T2 (de) 2006-03-16

Family

ID=25369725

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60202812T Expired - Lifetime DE60202812T2 (de) 2001-06-08 2002-06-07 Verwendung von Software-Unterbrechungsausnahmen in der Verwaltung von Übertragungen zwischen Prozessoren

Country Status (3)

Country Link
US (1) US20020178313A1 (de)
EP (1) EP1265148B1 (de)
DE (1) DE60202812T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6931643B2 (en) * 2000-04-03 2005-08-16 Texas Instruments Incorporated Interrupt throttling for inter-processor communications
US7680043B2 (en) * 2002-03-20 2010-03-16 International Business Machines Corporation Network processor having fast flow queue disable process
US6996699B2 (en) * 2002-09-10 2006-02-07 Microsoft Corporation Secondary processor execution kernel framework
US8984199B2 (en) * 2003-07-31 2015-03-17 Intel Corporation Inter-processor interrupts
KR100580836B1 (ko) * 2004-12-03 2006-05-16 한국전자통신연구원 직교주파수분할다중화 시스템의 송신 장치 및 그 방법
US9588804B2 (en) * 2014-01-21 2017-03-07 Qualcomm Incorporated System and method for synchronous task dispatch in a portable device
US20160034411A1 (en) * 2014-08-04 2016-02-04 Qualcomm Innovation Center, Inc. Subsystem Peripheral Ownership Scheduling and Reconfiguration for Highly Integrated System on Chips

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4209839A (en) * 1978-06-16 1980-06-24 International Business Machines Corporation Shared synchronous memory multiprocessing arrangement
US4604500A (en) * 1981-12-02 1986-08-05 At&T Bell Laboratories Multiprocessing interrupt arrangement
US4698753A (en) * 1982-11-09 1987-10-06 Texas Instruments Incorporated Multiprocessor interface device
GB2195038A (en) * 1986-07-05 1988-03-23 Narayanaswamy D Jayaram A multi-microprocessor system with confederate processors
JP3678759B2 (ja) * 1992-07-21 2005-08-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 割込を発生するための装置および割込を発生するための方法
CA2123447C (en) * 1993-09-20 1999-02-16 Richard L. Arndt Scalable system interrupt structure for a multiprocessing system
GB9505724D0 (en) * 1995-03-21 1995-05-10 Newbridge Networks Corp ATM without traffic shaping
US5996058A (en) * 1996-08-19 1999-11-30 Samsung Electronics Company, Ltd. System and method for handling software interrupts with argument passing
US6148361A (en) * 1998-12-17 2000-11-14 International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
US6651163B1 (en) * 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system

Also Published As

Publication number Publication date
US20020178313A1 (en) 2002-11-28
EP1265148B1 (de) 2005-02-02
DE60202812T2 (de) 2006-03-16
EP1265148A1 (de) 2002-12-11

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Legal Events

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8364 No opposition during term of opposition