DE60220590D1 - Verfahren zur Reduzierung von Kopplungseffekten zwischen multi-level Speicherelementen eines nicht flüchtigen Speichers - Google Patents

Verfahren zur Reduzierung von Kopplungseffekten zwischen multi-level Speicherelementen eines nicht flüchtigen Speichers

Info

Publication number
DE60220590D1
DE60220590D1 DE60220590T DE60220590T DE60220590D1 DE 60220590 D1 DE60220590 D1 DE 60220590D1 DE 60220590 T DE60220590 T DE 60220590T DE 60220590 T DE60220590 T DE 60220590T DE 60220590 D1 DE60220590 D1 DE 60220590D1
Authority
DE
Germany
Prior art keywords
memory
states
programming
volatile memory
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60220590T
Other languages
English (en)
Other versions
DE60220590T2 (de
Inventor
Jian Chen
Tomoharu Tanaka
Yupin Fong
Khandker N Quader
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
SanDisk Corp
Original Assignee
Toshiba Corp
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, SanDisk Corp filed Critical Toshiba Corp
Publication of DE60220590D1 publication Critical patent/DE60220590D1/de
Application granted granted Critical
Publication of DE60220590T2 publication Critical patent/DE60220590T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/12Programming voltage switching circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells
DE60220590T 2001-06-27 2002-06-26 Verfahren zur Reduzierung von Kopplungseffekten zwischen multi-level Speicherelementen eines nicht flüchtigen Speichers Expired - Lifetime DE60220590T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/893,277 US6522580B2 (en) 2001-06-27 2001-06-27 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
US893277 2001-06-27

Publications (2)

Publication Number Publication Date
DE60220590D1 true DE60220590D1 (de) 2007-07-26
DE60220590T2 DE60220590T2 (de) 2008-02-14

Family

ID=25401316

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60220590T Expired - Lifetime DE60220590T2 (de) 2001-06-27 2002-06-26 Verfahren zur Reduzierung von Kopplungseffekten zwischen multi-level Speicherelementen eines nicht flüchtigen Speichers

Country Status (8)

Country Link
US (4) US6522580B2 (de)
EP (2) EP1271553B1 (de)
JP (1) JP4221196B2 (de)
KR (1) KR100926950B1 (de)
CN (2) CN100350503C (de)
AT (1) ATE364885T1 (de)
DE (1) DE60220590T2 (de)
TW (1) TW583672B (de)

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US6522580B2 (en) 2003-02-18
EP1271553B1 (de) 2007-06-13
KR100926950B1 (ko) 2009-11-17
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US6807095B2 (en) 2004-10-19
ATE364885T1 (de) 2007-07-15
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US20030128586A1 (en) 2003-07-10
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