DE60238646D1 - Verfahren und vorrichtung zur bewertung und optimierung eines zeichengabesystems - Google Patents

Verfahren und vorrichtung zur bewertung und optimierung eines zeichengabesystems

Info

Publication number
DE60238646D1
DE60238646D1 DE60238646T DE60238646T DE60238646D1 DE 60238646 D1 DE60238646 D1 DE 60238646D1 DE 60238646 T DE60238646 T DE 60238646T DE 60238646 T DE60238646 T DE 60238646T DE 60238646 D1 DE60238646 D1 DE 60238646D1
Authority
DE
Germany
Prior art keywords
information
patterns
receive circuit
testing
signaling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60238646T
Other languages
English (en)
Inventor
Jared Zerbe
Pak Shing Chau
William Franklin Stonecypher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of DE60238646D1 publication Critical patent/DE60238646D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/32—Reducing cross-talk, e.g. by compensating
DE60238646T 2001-10-12 2002-10-11 Verfahren und vorrichtung zur bewertung und optimierung eines zeichengabesystems Expired - Lifetime DE60238646D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/976,170 US7137048B2 (en) 2001-02-02 2001-10-12 Method and apparatus for evaluating and optimizing a signaling system
PCT/US2002/032602 WO2003032652A2 (en) 2001-10-12 2002-10-11 Method and apparatus for evaluating and optimizing a signaling system

Publications (1)

Publication Number Publication Date
DE60238646D1 true DE60238646D1 (de) 2011-01-27

Family

ID=25523808

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60238646T Expired - Lifetime DE60238646D1 (de) 2001-10-12 2002-10-11 Verfahren und vorrichtung zur bewertung und optimierung eines zeichengabesystems

Country Status (6)

Country Link
US (2) US7137048B2 (de)
EP (2) EP2253964B1 (de)
AT (1) ATE491955T1 (de)
AU (1) AU2002334980A1 (de)
DE (1) DE60238646D1 (de)
WO (1) WO2003032652A2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7137048B2 (en) * 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7490275B2 (en) 2001-02-02 2009-02-10 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7231306B1 (en) 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
DE10221611B4 (de) * 2002-05-15 2013-01-24 Infineon Technologies Ag Digitalbaustein mit einer Selbsttestfunktion
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US7627029B2 (en) * 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
JP2007527110A (ja) * 2003-07-09 2007-09-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ オンボード特徴化ユニットを有するｉｃ
US7275195B2 (en) * 2003-10-03 2007-09-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Programmable built-in self-test circuit for serializer/deserializer circuits and method
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US20050154953A1 (en) * 2004-01-12 2005-07-14 Norskog Allen C. Multiple function pattern generator and comparator having self-seeding test function
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7158536B2 (en) * 2004-01-28 2007-01-02 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
US7404115B2 (en) * 2004-02-12 2008-07-22 International Business Machines Corporation Self-synchronising bit error analyser and circuit
US6961862B2 (en) 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US7921323B2 (en) * 2004-05-11 2011-04-05 L-3 Communications Integrated Systems, L.P. Reconfigurable communications infrastructure for ASIC networks
US7444454B2 (en) 2004-05-11 2008-10-28 L-3 Communications Integrated Systems L.P. Systems and methods for interconnection of multiple FPGA devices
US20060067391A1 (en) * 2004-09-30 2006-03-30 Rambus Inc. Methods and systems for margin testing high-speed communication channels
US7313738B2 (en) * 2005-02-17 2007-12-25 International Business Machines Corporation System and method for system-on-chip interconnect verification
TWI283351B (en) * 2005-05-06 2007-07-01 Primax Electronics Ltd Wireless peripheral system for computer
US7269524B1 (en) * 2006-06-30 2007-09-11 Inapac Technology, Inc. Delay lock loop delay adjusting method and apparatus
US7724852B2 (en) 2006-08-30 2010-05-25 Rambus Inc. Drift cancellation technique for use in clock-forwarding architectures
US7808995B2 (en) * 2006-11-16 2010-10-05 L-3 Communications Integrated Systems L.P. Methods and systems for relaying data packets
JP2008160235A (ja) * 2006-12-21 2008-07-10 Leader Electronics Corp チューナのビットエラーレート測定の方法及び装置
WO2009059169A2 (en) * 2007-10-31 2009-05-07 Richard Crosby Broadcast television distribution services architecture
US8024142B1 (en) 2007-12-20 2011-09-20 Pmc-Sierra Us, Inc. Method and system for analyzing signal waveforms
US7492807B1 (en) 2008-04-07 2009-02-17 International Business Machines Corporation Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods
WO2010078383A1 (en) * 2008-12-31 2010-07-08 Rambus Inc. Active calibration for high-speed memory devices
US8467436B1 (en) 2009-04-29 2013-06-18 Pmc-Sierra Us, Inc. DSP-based diagnostics for monitoring a SerDes link
US8368423B2 (en) * 2009-12-23 2013-02-05 L-3 Communications Integrated Systems, L.P. Heterogeneous computer architecture based on partial reconfiguration
US8397054B2 (en) * 2009-12-23 2013-03-12 L-3 Communications Integrated Systems L.P. Multi-phased computational reconfiguration
US8843794B2 (en) 2012-09-24 2014-09-23 Intel Corporation Method, system and apparatus for evaluation of input/output buffer circuitry
US9110134B2 (en) 2012-12-27 2015-08-18 Intel Corporation Input/output delay testing for devices utilizing on-chip delay generation
US9996439B2 (en) 2015-09-23 2018-06-12 Qualcomm Incorporated Self-error injection technique for point-to-point interconnect to increase test coverage
KR20220088159A (ko) 2020-12-18 2022-06-27 삼성전자주식회사 집적 회로 및 이의 동작 방법

Family Cites Families (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3869580A (en) 1971-11-15 1975-03-04 Milgo Electronic Corp Apparatus for testing data modems which simultaneously transmit and receive frequency multiplexed signals
US3909563A (en) 1973-11-06 1975-09-30 Wescom Procedure and apparatus for locating faults in digital repeatered lines
US7137048B2 (en) * 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
DE2838816A1 (de) 1978-09-06 1980-03-20 Tekade Felten & Guilleaume Schleifentest fuer datenuebertragungsstrecken
US4475201A (en) * 1981-06-11 1984-10-02 Photochemical Research Associates Inc. Longitudinally pumped dye laser arrangement
US4475210A (en) * 1982-02-26 1984-10-02 International Telephone And Telegraph Corporation Data eye monitor
FR2574201B1 (fr) 1984-11-30 1987-04-24 Cit Alcatel Procede et dispositif de telesignalisation pour une liaison de transmission numerique
EP0333942A1 (de) 1988-03-22 1989-09-27 Hewlett-Packard Limited Überwachung von digitalen Übertragungssystemen
US5483676A (en) * 1988-08-04 1996-01-09 Norand Corporation Mobile radio data communication system and method
US5084874A (en) * 1988-09-07 1992-01-28 Texas Instruments Incorporated Enhanced test circuit
US5142495A (en) 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
US5056094A (en) * 1989-06-09 1991-10-08 Texas Instruments Incorporated Delay fault testing method and apparatus
FI83007C (fi) * 1989-10-05 1991-05-10 Nokia Data Systems Digitalt dataoeverfoeringssystem.
US5265089A (en) 1990-01-30 1993-11-23 Nec Corporation Loopback test circuit
EP0456914B1 (de) * 1990-05-15 1994-12-14 BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap Einrichtung zur Bewertung der Übertragungsqualität
JP2925685B2 (ja) * 1990-08-02 1999-07-28 株式会社ニデック フレーム形状測定装置
US5258986A (en) 1990-09-19 1993-11-02 Vlsi Technology, Inc. Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
JPH04147071A (ja) 1990-10-09 1992-05-20 Nec Corp テスト回路
DE4102726C1 (en) * 1991-01-30 1992-04-23 Siemens Ag, 8000 Muenchen, De Self-testing appts. for function block coupling input words - has tow linear feedback shift registers clocked by respective external and internal clocks
JP2616593B2 (ja) 1991-01-31 1997-06-04 日本電気株式会社 パタン試験方式
US5228042A (en) * 1991-02-07 1993-07-13 Northern Telecom Limited Method and circuit for testing transmission paths
JP2723687B2 (ja) 1991-04-08 1998-03-09 シャープ株式会社 表示装置用駆動回路の試験装置
JP3265614B2 (ja) 1991-04-16 2002-03-11 松下電器産業株式会社 検査系列生成方法
JPH0519028A (ja) 1991-07-11 1993-01-26 Nec Corp 論理回路試験装置および論理回路の試験方法
US5197062A (en) 1991-09-04 1993-03-23 Picklesimer David D Method and system for simultaneous analysis of multiplexed channels
JP3025068B2 (ja) 1991-09-12 2000-03-27 富士通株式会社 Ａｔｍスイッチのパス試験方式
US5519719A (en) 1991-12-19 1996-05-21 Adc Telecommunications, Inc. Universal pattern generator
US5412665A (en) 1992-01-10 1995-05-02 International Business Machines Corporation Parallel operation linear feedback shift register
EP0578858A1 (de) 1992-07-17 1994-01-19 International Business Machines Corporation AC-Verbindungsprüfung für integrierte Schaltungsbausteine
EP0584385B1 (de) 1992-08-25 1996-11-06 International Business Machines Corporation Verfahren und System zum Testen eines integrierten Schaltkreises mit Abfragedesign
US5369755A (en) * 1992-09-08 1994-11-29 Alliedsignal Inc. Computer communication bus system using multiple content induced transaction overlap (CITO) communication channels
CA2100906C (en) 1992-09-18 2000-05-02 Michael Wayne Andrews Method and apparatus for data parity in a transmission system
US5726991A (en) * 1993-06-07 1998-03-10 At&T Global Information Solutions Company Integral bit error rate test system for serial data communication links
US5761212A (en) * 1993-07-01 1998-06-02 Cirrus Logic, Inc. Channel quality
US5790523A (en) 1993-09-17 1998-08-04 Scientific-Atlanta, Inc. Testing facility for a broadband communications system
JP3545437B2 (ja) 1993-09-20 2004-07-21 富士通株式会社 パケット交換試験方法及びその装置
JPH0795166A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd 伝送システムの試験装置
JP2792416B2 (ja) 1993-11-17 1998-09-03 日本電気株式会社 半導体集積回路
US5802073A (en) * 1994-09-23 1998-09-01 Vlsi Technology, Inc. Built-in self test functional system block for UTOPIA interface
FI97836C (fi) 1994-10-31 1997-02-25 Nokia Telecommunications Oy Menetelmä tietoliikenneyhteyden muodostamiseksi
US5761216A (en) * 1995-02-24 1998-06-02 Advantest Corp. Bit error measurement system
TW293208B (de) 1995-04-17 1996-12-11 Matsushita Electric Ind Co Ltd
US5732089A (en) * 1995-09-27 1998-03-24 Ando Electric Co., Ltd. Bit error measurement circuit
US5867507A (en) * 1995-12-12 1999-02-02 International Business Machines Corporation Testable programmable gate array and associated LSSD/deterministic test methodology
US6061817A (en) 1996-06-10 2000-05-09 Cypress Semiconductor Corp. Method and apparatus for generating test pattern for sequence detection
US6055297A (en) * 1996-08-02 2000-04-25 Northern Telecom Limited Reducing crosstalk between communications systems
US5742798A (en) * 1996-08-09 1998-04-21 International Business Machines Corporation Compensation of chip to chip clock skew
US5831996A (en) 1996-10-10 1998-11-03 Lucent Technologies Inc. Digital circuit test generator
KR100206128B1 (ko) 1996-10-21 1999-07-01 윤종용 선형 궤환 쉬프트레지스터, 다중 입력기호 레지스터 및 이들을 이용한 내장 자기 진단회로
US6160790A (en) 1996-12-31 2000-12-12 Paradyne Corporation Crosstalk canceller system and method
US5815017A (en) * 1997-03-03 1998-09-29 Motorola, Inc. Forced oscillator circuit and method
US6331787B1 (en) * 1997-05-07 2001-12-18 California Micro Devices Corporation Termination circuits and methods therefor
US6097323A (en) * 1997-05-21 2000-08-01 Fujitsu Limited Serial/parallel converter using holding and latch flip-flops
US6073263A (en) 1997-10-29 2000-06-06 Credence Systems Corporation Parallel processing pattern generation system for an integrated circuit tester
US6341142B2 (en) * 1997-12-16 2002-01-22 Lsi Logic Corporation Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method
US6003118A (en) * 1997-12-16 1999-12-14 Acer Laboratories Inc. Method and apparatus for synchronizing clock distribution of a data processing system
US6154659A (en) * 1997-12-24 2000-11-28 Nortel Networks Limited Fast forward link power control in a code division multiple access system
JP3778397B2 (ja) * 1997-12-27 2006-05-24 ソニー株式会社 送信方法、送信電力制御方法及び基地局装置
US6269451B1 (en) * 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
JPH11272509A (ja) * 1998-03-24 1999-10-08 Nec Ic Microcomput Syst Ltd 半導体集積回路
US6201829B1 (en) * 1998-04-03 2001-03-13 Adaptec, Inc. Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator
EP0961437A1 (de) * 1998-05-29 1999-12-01 Alcatel Methode zur Messung der Bitfehlerhaüfigkeit in einem zellbasierten Telekommunikationssystem
US6222380B1 (en) * 1998-06-15 2001-04-24 International Business Machines Corporation High speed parallel/serial link for data communication
JP2000021193A (ja) 1998-07-01 2000-01-21 Fujitsu Ltd メモリ試験方法及び装置並びに記憶媒体
JP2000022600A (ja) 1998-07-07 2000-01-21 Fujitsu Ltd 時間領域等化器のトレーニング方法及びディジタルデータ伝送装置
JP2000035831A (ja) 1998-07-21 2000-02-02 Nec Corp 可変閾値電圧トランジスタを用いた低スキュークロックツリー回路
US6463109B1 (en) * 1998-08-25 2002-10-08 Vitesse Semiconductor Corporation Multiple channel adaptive data recovery system
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6181210B1 (en) * 1998-09-21 2001-01-30 Broadcom Corporation Low offset and low glitch energy charge pump for PLL-based timing recovery systems
US6631486B1 (en) * 1998-09-29 2003-10-07 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and method for testing the same
US6385236B1 (en) 1998-10-05 2002-05-07 Lsi Logic Corporation Method and Circuit for testing devices with serial data links
US6438159B1 (en) 1999-02-16 2002-08-20 Maxtor Corporation Method and apparatus for margining error rate of multi-drop data buses
US6292116B1 (en) 1999-05-17 2001-09-18 Altera Corporation Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit
US6421801B1 (en) * 1999-06-08 2002-07-16 Intel Corporation Testing IO timing in a delay locked system using separate transmit and receive loops
US20010021987A1 (en) 1999-07-14 2001-09-13 Madabusi Govindarajan Method and apparatus for performance monitoring of data transparent communication links
US6473871B1 (en) 1999-08-31 2002-10-29 Sun Microsystems, Inc. Method and apparatus for HASS testing of busses under programmable control
JP4371488B2 (ja) 1999-09-03 2009-11-25 富士通マイクロエレクトロニクス株式会社 デバイス試験評価システムおよびデバイス試験評価方法
US6650698B1 (en) * 1999-09-29 2003-11-18 Conexant Systems, Inc. Non-linear equalization for the upstream data connection of 56K PCM modems
US6694466B1 (en) 1999-10-27 2004-02-17 Agere Systems Inc. Method and system for improving the test quality for scan-based BIST using a general test application scheme
US6628621B1 (en) * 1999-11-02 2003-09-30 Adtran Inc. Multichannel-capable bit error rate test system
US6834367B2 (en) * 1999-12-22 2004-12-21 International Business Machines Corporation Built-in self test system and method for high speed clock and data recovery circuit
US6477674B1 (en) 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
JP2001197043A (ja) 2000-01-07 2001-07-19 Fujitsu Ltd 同符号連続耐力試験装置
US6542538B2 (en) 2000-01-10 2003-04-01 Qualcomm Incorporated Method and apparatus for testing wireless communication channels
AU2001227892A1 (en) 2000-01-14 2001-07-24 Parthus Technologies Plc An algorithmic test pattern generator, with built-in-self-test (bist) capabilities, for functional testing of a circuit
US6574758B1 (en) * 2000-03-10 2003-06-03 Cisco Technology, Inc. Testing a bus coupled between two electronic devices
GB0006291D0 (en) 2000-03-15 2000-05-03 Lucent Technologies Inc Data communication link
US6606041B1 (en) * 2000-05-10 2003-08-12 Micron Technology, Inc. Predictive timing calibration for memory devices
US6615148B2 (en) * 2000-05-17 2003-09-02 Tektronix, Inc. Streaming distributed test and measurement instrument
JP3512728B2 (ja) 2000-09-13 2004-03-31 Ｎｅｃマイクロシステム株式会社 論理回路のテストパタン生成方法及び装置
JP3851766B2 (ja) * 2000-09-29 2006-11-29 株式会社ルネサステクノロジ 半導体集積回路
US6674998B2 (en) * 2000-10-02 2004-01-06 Intersil Americas Inc. System and method for detecting and correcting phase error between differential signals
US6671847B1 (en) * 2000-11-08 2003-12-30 Intel Corporation I/O device testing method and apparatus
JP2002152317A (ja) 2000-11-10 2002-05-24 Fujitsu Ltd 試験装置
US6625764B1 (en) 2000-11-28 2003-09-23 Nortel Networks Limited Testing using test packets containing random data
JP3937034B2 (ja) 2000-12-13 2007-06-27 株式会社日立製作所 半導体集積回路のテスト方法及びテストパターン発生回路
US6684351B1 (en) * 2000-12-22 2004-01-27 Applied Micro Circuits Corporation System and method for diagnosing errors in multidimensional digital frame structure communications
US6684350B1 (en) 2000-12-22 2004-01-27 Cisco Technology, Inc. Repetitive pattern testing circuit for AC-coupled systems
US6651205B2 (en) 2001-02-02 2003-11-18 Advantest Corp. Test pattern conversion apparatus and conversion method
US6873939B1 (en) * 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US6769084B2 (en) 2001-03-13 2004-07-27 Samsung Electronics Co., Ltd. Built-in self test circuit employing a linear feedback shift register
JP2003005831A (ja) 2001-06-20 2003-01-08 Nippon Yusoki Co Ltd 接触検出装置
DE60138378D1 (de) 2001-08-15 2009-05-28 Psytechnics Ltd Messung der Genauigkeit eines Kanals
JP2003078486A (ja) * 2001-08-31 2003-03-14 Mitsubishi Electric Corp 光送受信器、多重化集積回路、多重分離集積回路、一体型多重化／多重分離集積回路及び光送受信器の評価・試験方法
JP2003121499A (ja) 2001-10-09 2003-04-23 Hitachi Ltd 組込みテスト機能付き半導体集積回路、テストコード生成プログラムから成る電子設計データを保存する記憶媒体、該半導体集積回路のテスト方法、テストコード生成自動化方法及びそのプログラム

Also Published As

Publication number Publication date
US20060236183A1 (en) 2006-10-19
WO2003032652A2 (en) 2003-04-17
EP1588571A2 (de) 2005-10-26
EP1588571A4 (de) 2007-11-14
EP2253964A2 (de) 2010-11-24
EP1588571B1 (de) 2010-12-15
US7360127B2 (en) 2008-04-15
AU2002334980A8 (en) 2006-11-09
US7137048B2 (en) 2006-11-14
EP2253964B1 (de) 2012-08-22
WO2003032652A3 (en) 2006-08-17
EP2253964A3 (de) 2011-03-09
ATE491955T1 (de) 2011-01-15
AU2002334980A1 (en) 2003-04-22
US20030208707A9 (en) 2003-11-06
US20030084385A1 (en) 2003-05-01

Similar Documents

Publication Publication Date Title
DE60238646D1 (de) Verfahren und vorrichtung zur bewertung und optimierung eines zeichengabesystems
ATE433623T1 (de) Verfahren und vorrichtung zum testen optischer netzwerke
US7136773B2 (en) Testing apparatus and testing method
DE69030015T2 (de) Verfahren und Vorrichtung zur Prüfung von integrierten Schaltungen mit zahlreichen Anschlüssen
ATE224061T1 (de) Verfahren und vorrichtung zum prüfen von gedruckten leiterplatten
WO2004077524A3 (en) Method and apparatus for test and characterization of semiconductor components
MY124258A (en) Method of testing electronic components and testing apparatus for electronic components
DE602006015025D1 (de) Verfahren und Vorrichtung zum Testen des Übersprechens in einer Kommunikationsleitung mit mehreren Teilnehmern
ATE314657T1 (de) Verfahren und vorrichtung zum prüfen von leiterplatten
DE60227308D1 (de) System, Verfahren und Vorrichtung zur Bestimmung der Grenze eines Informationselements
ATE483584T1 (de) Prüfmittel und verfahren zur kontrolle des offset-und digitaldrucks
TW200519906A (en) Data recording method, data recording device, and recording medium for program recording
Menon et al. Redundancy removal and simplification of combinational circuits
SE9602564L (sv) Kretskortstest
JPH0519028A (ja) 論理回路試験装置および論理回路の試験方法
DE59814107D1 (de) Verfahren und Vorrichtung zur Beurteilung der Übertragungsqualität
Kalpana et al. A novel specification based test pattern generation using genetic algorithm and wavelets
JP2003227777A (ja) マルチポート光学装置の測定
ATE364961T1 (de) Verfahren zum testen einer teilnehmerleitungsschnittstelle, welche eine hybridschaltung enthält, und entsprechende vorrichtung
DE69929300D1 (de) Verfahren und Anordnung zur kombinierten Schwingungsmessung
EP1239293A3 (de) Anordnung und Verfahren zum Testen von integrierten Schaltkreisen
DE602004003760D1 (de) Verfahren und Vorrichtung zur Analyse eines über eine Kommunikationsverbindung gesendeten Signals
TWI789091B (zh) 電子系統測試方法
KR101717690B1 (ko) 디임베딩을 위한 테스트 픽스처 추출 방법
EP3429098A1 (de) Sonde, messsystem, verfahren zum testen von signalen sowie verfahren zur einstellung einer sonde