DE60324275D1 - Nichtflüchtiges cmos latch mit mehreren schwellwerten und leckstromkontrolle - Google Patents

Nichtflüchtiges cmos latch mit mehreren schwellwerten und leckstromkontrolle

Info

Publication number
DE60324275D1
DE60324275D1 DE60324275T DE60324275T DE60324275D1 DE 60324275 D1 DE60324275 D1 DE 60324275D1 DE 60324275 T DE60324275 T DE 60324275T DE 60324275 T DE60324275 T DE 60324275T DE 60324275 D1 DE60324275 D1 DE 60324275D1
Authority
DE
Germany
Prior art keywords
latch
circuits
voltage threshold
signal path
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324275T
Other languages
English (en)
Inventor
Mehdi Hamidi Sani
Gregory A Uvieghara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of DE60324275D1 publication Critical patent/DE60324275D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
DE60324275T 2002-05-24 2003-05-23 Nichtflüchtiges cmos latch mit mehreren schwellwerten und leckstromkontrolle Expired - Lifetime DE60324275D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/155,378 US6794914B2 (en) 2002-05-24 2002-05-24 Non-volatile multi-threshold CMOS latch with leakage control
PCT/US2003/016055 WO2003100830A2 (en) 2002-05-24 2003-05-23 Non-volatile multi-threshold cmos latch with leakage control

Publications (1)

Publication Number Publication Date
DE60324275D1 true DE60324275D1 (de) 2008-12-04

Family

ID=29549050

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324275T Expired - Lifetime DE60324275D1 (de) 2002-05-24 2003-05-23 Nichtflüchtiges cmos latch mit mehreren schwellwerten und leckstromkontrolle

Country Status (10)

Country Link
US (1) US6794914B2 (de)
EP (1) EP1510006B1 (de)
JP (1) JP2005527166A (de)
AT (1) ATE412268T1 (de)
AU (1) AU2003273139A1 (de)
CA (1) CA2487363A1 (de)
DE (1) DE60324275D1 (de)
HK (1) HK1075139A1 (de)
RU (1) RU2321944C2 (de)
WO (1) WO2003100830A2 (de)

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989702B2 (en) * 2002-07-11 2006-01-24 Texas Instruments Incorporated Retention register with normal functionality independent of retention power supply
US7091766B2 (en) * 2002-07-11 2006-08-15 Texas Instruments Incorporated Retention register for system-transparent state retention
DE10255636B4 (de) * 2002-11-28 2010-12-02 Infineon Technologies Ag Schaltkreis-Anordnung
US7294877B2 (en) 2003-03-28 2007-11-13 Nantero, Inc. Nanotube-on-gate FET structures and applications
WO2005019793A2 (en) 2003-05-14 2005-03-03 Nantero, Inc. Sensor platform using a horizontally oriented nanotube element
US7115901B2 (en) 2003-06-09 2006-10-03 Nantero, Inc. Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
US7274064B2 (en) 2003-06-09 2007-09-25 Nanatero, Inc. Non-volatile electromechanical field effect devices and circuits using same and methods of forming same
US6946903B2 (en) * 2003-07-28 2005-09-20 Elixent Limited Methods and systems for reducing leakage current in semiconductor circuits
CA2535634A1 (en) 2003-08-13 2005-05-26 Nantero, Inc Nanotube-based switching elements with multiple controls and circuits made from same
US7289357B2 (en) 2003-08-13 2007-10-30 Nantero, Inc. Isolation structure for deflectable nanotube elements
JP2005157620A (ja) * 2003-11-25 2005-06-16 Matsushita Electric Ind Co Ltd 半導体集積回路
US7103857B2 (en) * 2003-12-09 2006-09-05 International Business Machines Corporation Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices
US7528437B2 (en) * 2004-02-11 2009-05-05 Nantero, Inc. EEPROMS using carbon nanotubes for cell storage
KR20050099259A (ko) * 2004-04-09 2005-10-13 삼성전자주식회사 고속 플립플롭들 및 이를 이용한 복합 게이트들
US7075175B2 (en) 2004-04-22 2006-07-11 Qualcomm Incorporated Systems and methods for testing packaged dies
KR101045295B1 (ko) * 2004-04-29 2011-06-29 삼성전자주식회사 Ｍｔｃｍｏｓ 플립-플롭, 그를 포함하는 ｍｔｃｍｏｓ회로, 및 그 생성 방법
JP2005323295A (ja) * 2004-05-11 2005-11-17 Asahi Kasei Microsystems Kk ラッチ回路及びフリップフロップ回路
JP2006005661A (ja) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd フリップフロップ回路
US7161403B2 (en) * 2004-06-18 2007-01-09 Nantero, Inc. Storage elements using nanotube switching elements
US7652342B2 (en) 2004-06-18 2010-01-26 Nantero, Inc. Nanotube-based transfer devices and related circuits
US7164744B2 (en) 2004-06-18 2007-01-16 Nantero, Inc. Nanotube-based logic driver circuits
US7288970B2 (en) 2004-06-18 2007-10-30 Nantero, Inc. Integrated nanotube and field effect switching device
TWI399864B (zh) 2004-09-16 2013-06-21 Nantero Inc 使用奈米管之發光體及其製造方法
US7248090B2 (en) 2005-01-10 2007-07-24 Qualcomm, Incorporated Multi-threshold MOS circuits
US7598544B2 (en) * 2005-01-14 2009-10-06 Nanotero, Inc. Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same
US8362525B2 (en) * 2005-01-14 2013-01-29 Nantero Inc. Field effect device having a channel of nanofabric and methods of making same
US7180348B2 (en) * 2005-03-24 2007-02-20 Arm Limited Circuit and method for storing data in operational and sleep modes
US7394687B2 (en) 2005-05-09 2008-07-01 Nantero, Inc. Non-volatile-shadow latch using a nanotube switch
US7479654B2 (en) 2005-05-09 2009-01-20 Nantero, Inc. Memory arrays using nanotube articles with reprogrammable resistance
TWI324773B (en) 2005-05-09 2010-05-11 Nantero Inc Non-volatile shadow latch using a nanotube switch
US7781862B2 (en) 2005-05-09 2010-08-24 Nantero, Inc. Two-terminal nanotube devices and systems and methods of making same
US20070008004A1 (en) * 2005-07-11 2007-01-11 Vikram Santurkar Apparatus and methods for low-power routing circuitry in programmable logic devices
US7342287B2 (en) * 2005-07-19 2008-03-11 International Business Machines Corporation Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures
KR100733447B1 (ko) * 2005-09-28 2007-06-29 주식회사 하이닉스반도체 누설전류 방지를 위한 메모리장치의 데이터 출력 멀티플렉서
US7391249B2 (en) * 2005-12-07 2008-06-24 Electronics And Telecommunications Research Institute Multi-threshold CMOS latch circuit
KR100702364B1 (ko) 2005-12-07 2007-04-02 한국전자통신연구원 Ｍｔｃｍｏｓ 래치회로
US7420403B2 (en) * 2005-12-08 2008-09-02 Electronics And Telecommunications Research Institute Latch circuit and flip-flop
KR100810501B1 (ko) * 2005-12-08 2008-03-07 한국전자통신연구원 광대역 다중모드 주파수 합성기 및 가변 분주기
US7366036B2 (en) * 2006-01-13 2008-04-29 International Business Machines Corporation Memory device with control circuit for regulating power supply voltage
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US7932545B2 (en) * 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7310278B2 (en) * 2006-05-04 2007-12-18 International Business Machines Corporation Method and apparatus for in-system redundant array repair on integrated circuits
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
KR101332925B1 (ko) * 2007-08-13 2013-11-26 에이저 시스템즈 엘엘시 메모리 장치, 집적 회로, 메모리 장치에서 사용되는 방법 및 컴퓨터 판독가능 저장 매체
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101739709B1 (ko) 2008-07-16 2017-05-24 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8209573B2 (en) * 2008-12-22 2012-06-26 Lsi Corporation Sequential element low power scan implementation
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8471618B2 (en) 2010-04-12 2013-06-25 Mediatek Inc. Flip-flop for low swing clock signal
US8228109B2 (en) * 2010-06-28 2012-07-24 Freescale Semiconductor, Inc. Transmission gate circuitry for high voltage terminal
KR101794261B1 (ko) * 2010-11-11 2017-11-08 삼성전자주식회사 래치 회로, 그것을 포함하는 플립플롭 및 데이터 래치 방법
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8207755B1 (en) * 2011-02-15 2012-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Low leakage power detection circuit
US20120223756A1 (en) * 2011-03-01 2012-09-06 Morteza Afghahi Method and System for High Speed, Low Power and Small Flip-Flops
US8390328B2 (en) 2011-05-13 2013-03-05 Arm Limited Supplying a clock signal and a gated clock signal to synchronous elements
WO2013106687A2 (en) * 2012-01-13 2013-07-18 The Board Of Trustees Of The University Of Arkansas Multi-threshold sleep convention logic without nsleep
US8957716B2 (en) * 2012-11-21 2015-02-17 Broadcom Corporation Multiple threshold voltage standard cells
US8836398B2 (en) * 2013-02-05 2014-09-16 Texas Instruments Incorporated Negative edge flip-flop with dual-port slave latch
US8836399B2 (en) * 2013-02-05 2014-09-16 Texas Instruments Incorporated Positive edge flip-flop with dual-port slave latch
US9099998B2 (en) * 2013-02-19 2015-08-04 Texas Instruments Incorporated Positive edge preset reset flip-flop with dual-port slave latch
US9348402B2 (en) * 2013-02-19 2016-05-24 Qualcomm Incorporated Multiple critical paths having different threshold voltages in a single processor core
US8970188B2 (en) * 2013-04-05 2015-03-03 Synaptics Incorporated Adaptive frequency compensation for high speed linear voltage regulator
US9673786B2 (en) * 2013-04-12 2017-06-06 Qualcomm Incorporated Flip-flop with reduced retention voltage
US9287858B1 (en) * 2014-09-03 2016-03-15 Texas Instruments Incorporated Low leakage shadow latch-based multi-threshold CMOS sequential circuit
CN106160717B (zh) 2015-04-03 2020-08-18 恩智浦美国有限公司 传输门电路
US9933800B1 (en) 2016-09-30 2018-04-03 Synaptics Incorporated Frequency compensation for linear regulators
US11165430B1 (en) 2020-12-21 2021-11-02 Kepler Computing Inc. Majority logic gate based sequential circuit
US11303280B1 (en) 2021-08-19 2022-04-12 Kepler Computing Inc. Ferroelectric or paraelectric based sequential circuit
JP2023034195A (ja) 2021-08-30 2023-03-13 キオクシア株式会社 フリップフロップ回路、及び非同期受け回路
CN114253341B (zh) * 2021-12-22 2023-03-14 江苏集萃智能集成电路设计技术研究所有限公司 一种输出电路和电压缓冲器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982211A (en) * 1997-03-31 1999-11-09 Texas Instruments Incorporated Hybrid dual threshold transistor registers
JP3499748B2 (ja) * 1998-06-12 2004-02-23 Ｎｅｃエレクトロニクス株式会社 順序回路
JP2000114935A (ja) * 1998-10-02 2000-04-21 Nec Corp 順序回路
US6231147B1 (en) * 1999-04-19 2001-05-15 Texas Instruments Incorporated Data storage circuits using a low threshold voltage output enable circuit
JP3614125B2 (ja) * 2000-10-23 2005-01-26 三星電子株式会社 Ｃｐフリップフロップ
JP3548115B2 (ja) * 2000-12-26 2004-07-28 株式会社東芝 半導体集積回路及び半導体集積回路装置
US6538471B1 (en) * 2001-10-10 2003-03-25 International Business Machines Corporation Multi-threshold flip-flop circuit having an outside feedback

Also Published As

Publication number Publication date
AU2003273139A8 (en) 2003-12-12
WO2003100830A3 (en) 2004-10-07
ATE412268T1 (de) 2008-11-15
RU2321944C2 (ru) 2008-04-10
US20030218231A1 (en) 2003-11-27
WO2003100830A2 (en) 2003-12-04
JP2005527166A (ja) 2005-09-08
RU2004137817A (ru) 2005-06-10
US6794914B2 (en) 2004-09-21
EP1510006A2 (de) 2005-03-02
CA2487363A1 (en) 2003-12-04
AU2003273139A1 (en) 2003-12-12
EP1510006B1 (de) 2008-10-22
HK1075139A1 (en) 2005-12-02

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