DE60324888D1 - und Herstellungsverfahren - Google Patents

und Herstellungsverfahren

Info

Publication number
DE60324888D1
DE60324888D1 DE60324888T DE60324888T DE60324888D1 DE 60324888 D1 DE60324888 D1 DE 60324888D1 DE 60324888 T DE60324888 T DE 60324888T DE 60324888 T DE60324888 T DE 60324888T DE 60324888 D1 DE60324888 D1 DE 60324888D1
Authority
DE
Germany
Prior art keywords
manufacturing process
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324888T
Other languages
English (en)
Inventor
Sheng Teng Hsu
Wei Pan
Weiwei Zhuang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE60324888D1 publication Critical patent/DE60324888D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
DE60324888T 2003-01-23 2003-12-24 und Herstellungsverfahren Expired - Lifetime DE60324888D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/350,643 US6875651B2 (en) 2003-01-23 2003-01-23 Dual-trench isolated crosspoint memory array and method for fabricating same

Publications (1)

Publication Number Publication Date
DE60324888D1 true DE60324888D1 (de) 2009-01-08

Family

ID=32594948

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324888T Expired - Lifetime DE60324888D1 (de) 2003-01-23 2003-12-24 und Herstellungsverfahren

Country Status (7)

Country Link
US (2) US6875651B2 (de)
EP (1) EP1441391B1 (de)
JP (1) JP4651075B2 (de)
KR (1) KR100580901B1 (de)
CN (1) CN1303665C (de)
DE (1) DE60324888D1 (de)
TW (1) TWI239591B (de)

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US20060081467A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima Systems and methods for magnetron deposition
US20060081466A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima High uniformity 1-D multiple magnet magnetron source
US7425504B2 (en) * 2004-10-15 2008-09-16 4D-S Pty Ltd. Systems and methods for plasma etching
KR100593750B1 (ko) * 2004-11-10 2006-06-28 삼성전자주식회사 이성분계 금속 산화막을 데이터 저장 물질막으로 채택하는교차점 비휘발성 기억소자 및 그 제조방법
JP4880894B2 (ja) * 2004-11-17 2012-02-22 シャープ株式会社 半導体記憶装置の構造及びその製造方法
US20130082232A1 (en) 2011-09-30 2013-04-04 Unity Semiconductor Corporation Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells
US20070084716A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile data storage
US20070084717A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile caching data storage
KR100723419B1 (ko) * 2006-02-17 2007-05-30 삼성전자주식회사 불휘발성 메모리소자 및 그 동작방법
US8395199B2 (en) * 2006-03-25 2013-03-12 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
KR100785509B1 (ko) * 2006-06-19 2007-12-13 한양대학교 산학협력단 ＲｅＲＡＭ 소자 및 그 제조 방법
US7932548B2 (en) 2006-07-14 2011-04-26 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US20080011603A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Ultra high vacuum deposition of PCMO material
US8454810B2 (en) * 2006-07-14 2013-06-04 4D-S Pty Ltd. Dual hexagonal shaped plasma source
TWI299162B (en) * 2006-07-18 2008-07-21 Ind Tech Res Inst Sensing memory device
TWI328871B (en) * 2006-09-04 2010-08-11 Ind Tech Res Inst Resistance type memory device
US8308915B2 (en) 2006-09-14 2012-11-13 4D-S Pty Ltd. Systems and methods for magnetron deposition
KR100780964B1 (ko) * 2006-11-13 2007-12-03 삼성전자주식회사 셀 다이오드를 구비하는 상변화 메모리 소자 및 그의제조방법
US8093578B2 (en) * 2006-11-20 2012-01-10 Panasonic Corporation Nonvolatile memory element, nonvolatile memory element array, and method for manufacturing nonvolatile memory element
KR100791008B1 (ko) * 2006-12-26 2008-01-04 삼성전자주식회사 서로 인접하는 셀들에 공유된 상변화 물질 패턴을 구비하는상변화 메모리 소자 및 이를 구비하는 전자제품
US8513637B2 (en) * 2007-07-13 2013-08-20 Macronix International Co., Ltd. 4F2 self align fin bottom electrodes FET drive phase change memory
US7704849B2 (en) 2007-12-03 2010-04-27 Micron Technology, Inc. Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
US8154005B2 (en) * 2008-06-13 2012-04-10 Sandisk 3D Llc Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars
KR20100070557A (ko) * 2008-12-18 2010-06-28 주식회사 동부하이텍 반도체 소자의 제조 방법
US8357601B2 (en) 2010-02-09 2013-01-22 Micron Technology, Inc. Cross-hair cell wordline formation
US20120012897A1 (en) * 2010-07-16 2012-01-19 Unity Semiconductor Corporation Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same
US8377718B2 (en) 2010-11-10 2013-02-19 Micron Technology, Inc. Methods of forming a crystalline Pr1-xCaxMnO3 (PCMO) material and methods of forming semiconductor device structures comprising crystalline PCMO
CN102201359B (zh) * 2011-05-27 2015-04-01 上海华虹宏力半导体制造有限公司 双沟槽隔离结构的形成方法
JP5671413B2 (ja) * 2011-06-07 2015-02-18 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置及びその製造方法
CN102280404B (zh) * 2011-08-01 2016-06-29 上海华虹宏力半导体制造有限公司 双沟槽隔离结构的形成方法
CN102254854B (zh) * 2011-08-01 2016-06-01 上海华虹宏力半导体制造有限公司 双沟槽隔离结构的形成方法
US8610099B2 (en) 2011-08-15 2013-12-17 Unity Semiconductor Corporation Planar resistive memory integration
US9806129B2 (en) 2014-02-25 2017-10-31 Micron Technology, Inc. Cross-point memory and methods for fabrication of same
US11223014B2 (en) 2014-02-25 2022-01-11 Micron Technology, Inc. Semiconductor structures including liners comprising alucone and related methods
US9484196B2 (en) 2014-02-25 2016-11-01 Micron Technology, Inc. Semiconductor structures including liners comprising alucone and related methods
US9577010B2 (en) 2014-02-25 2017-02-21 Micron Technology, Inc. Cross-point memory and methods for fabrication of same
US10249819B2 (en) 2014-04-03 2019-04-02 Micron Technology, Inc. Methods of forming semiconductor structures including multi-portion liners
US9768378B2 (en) 2014-08-25 2017-09-19 Micron Technology, Inc. Cross-point memory and methods for fabrication of same
US9748311B2 (en) 2014-11-07 2017-08-29 Micron Technology, Inc. Cross-point memory and methods for fabrication of same
TWI572074B (zh) * 2015-02-04 2017-02-21 力晶科技股份有限公司 電阻式隨機存取記憶體及其製造方法
KR102511693B1 (ko) * 2016-03-22 2023-03-20 삼성전자주식회사 반도체 메모리 소자 및 이의 제조 방법
US11495293B2 (en) * 2020-02-04 2022-11-08 Micron Technology, Inc. Configurable resistivity for lines in a memory device

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Also Published As

Publication number Publication date
KR20040068024A (ko) 2004-07-30
US20050136602A1 (en) 2005-06-23
JP2004228561A (ja) 2004-08-12
US6875651B2 (en) 2005-04-05
US7042066B2 (en) 2006-05-09
EP1441391A2 (de) 2004-07-28
EP1441391A3 (de) 2006-08-09
EP1441391B1 (de) 2008-11-26
CN1521826A (zh) 2004-08-18
US20040147081A1 (en) 2004-07-29
CN1303665C (zh) 2007-03-07
JP4651075B2 (ja) 2011-03-16
TWI239591B (en) 2005-09-11
TW200426979A (en) 2004-12-01
KR100580901B1 (ko) 2006-05-17

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