DE60324983D1 - Vorrichtung und Verfahren zur Erweiterung von Adressen in einem Mikroprozessor - Google Patents

Vorrichtung und Verfahren zur Erweiterung von Adressen in einem Mikroprozessor

Info

Publication number
DE60324983D1
DE60324983D1 DE60324983T DE60324983T DE60324983D1 DE 60324983 D1 DE60324983 D1 DE 60324983D1 DE 60324983 T DE60324983 T DE 60324983T DE 60324983 T DE60324983 T DE 60324983T DE 60324983 D1 DE60324983 D1 DE 60324983D1
Authority
DE
Germany
Prior art keywords
microprocessor
addresses
expanding
expanding addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324983T
Other languages
English (en)
Inventor
G Glenn Henry
Terry Parks
Rodney E Hooker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IP First LLC
Original Assignee
IP First LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IP First LLC filed Critical IP First LLC
Application granted granted Critical
Publication of DE60324983D1 publication Critical patent/DE60324983D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
DE60324983T 2002-04-15 2003-03-19 Vorrichtung und Verfahren zur Erweiterung von Adressen in einem Mikroprozessor Expired - Lifetime DE60324983D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37322902P 2002-04-15 2002-04-15
US10/227,571 US7380109B2 (en) 2002-04-15 2002-08-22 Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor

Publications (1)

Publication Number Publication Date
DE60324983D1 true DE60324983D1 (de) 2009-01-15

Family

ID=28794139

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324983T Expired - Lifetime DE60324983D1 (de) 2002-04-15 2003-03-19 Vorrichtung und Verfahren zur Erweiterung von Adressen in einem Mikroprozessor

Country Status (3)

Country Link
US (1) US7380109B2 (de)
EP (1) EP1359502B1 (de)
DE (1) DE60324983D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7380103B2 (en) 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US8719837B2 (en) 2004-05-19 2014-05-06 Synopsys, Inc. Microprocessor architecture having extendible logic
US7788420B2 (en) * 2005-09-22 2010-08-31 Lsi Corporation Address buffer mode switching for varying request sizes
US20070073925A1 (en) 2005-09-28 2007-03-29 Arc International (Uk) Limited Systems and methods for synchronizing multiple processing engines of a microprocessor
US7971034B2 (en) * 2008-03-19 2011-06-28 International Business Machines Corporation Reduced overhead address mode change management in a pipelined, recycling microprocessor
US8060724B2 (en) * 2008-08-15 2011-11-15 Freescale Semiconductor, Inc. Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
US8380914B1 (en) * 2008-12-31 2013-02-19 Micron Technology, Inc. Extended address mode for serial flash memory
TWI405215B (zh) * 2009-04-15 2013-08-11 Macronix Int Co Ltd 位址訊號傳輸方法及記憶體系統
US10163187B2 (en) * 2009-10-30 2018-12-25 Intel Corproation Graphics rendering using a hierarchical acceleration structure
US8538718B2 (en) 2010-12-14 2013-09-17 International Business Machines Corporation Clock edge grouping for at-speed test
US9396056B2 (en) * 2014-03-15 2016-07-19 Intel Corporation Conditional memory fault assist suppression
US10338943B1 (en) * 2015-09-17 2019-07-02 Symantec Corporation Techniques for emulating microprocessor instructions
US11119777B1 (en) * 2020-04-22 2021-09-14 International Business Machines Corporation Extended prefix including routing bit for extended instruction format

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
US4064554A (en) 1976-08-16 1977-12-20 Texas Instruments Incorporated Microcomputer with code conversion
US4217638A (en) 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
JPS57157362A (en) 1981-03-25 1982-09-28 Hitachi Ltd Method and apparatus of execution path career data pickup for architecture program
US4547849A (en) 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
JPS6491228A (en) 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
US5218712A (en) 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
US5448744A (en) 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
JPH04306735A (ja) 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
EP0550289A3 (en) 1992-01-02 1993-11-10 Amdahl Corp A mechanism to detect stores into the instruction stream
JP3644959B2 (ja) 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5481684A (en) 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5687338A (en) 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
ZA954460B (en) 1994-09-30 1996-02-05 Intel Corp Method and apparatus for processing memory-type information within a microprocessor
KR100374803B1 (ko) * 1995-05-25 2003-05-12 삼성전자주식회사 튜닝포크형자이로스코프
US5768574A (en) 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5822778A (en) 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
WO1997022922A1 (en) 1995-12-15 1997-06-26 Intel Corporation Instruction encoding techniques for microcontroller architecture
US5826089A (en) 1996-01-04 1998-10-20 Advanced Micro Devices, Inc. Instruction translation unit configured to translate from a first instruction set to a second instruction set
JP3663710B2 (ja) 1996-01-17 2005-06-22 ヤマハ株式会社 プログラムの生成方法およびプロセッサの割込制御方法
US5857103A (en) 1996-06-14 1999-01-05 Sun Microsystems, Inc. Method and apparatus for addressing extended registers on a processor in a computer system
US5778220A (en) 1996-11-18 1998-07-07 Intel Corporation Method and apparatus for disabling interrupts in a highly pipelined processor
JPH10161871A (ja) 1996-11-28 1998-06-19 Toshiba Corp プロセッサ
US5937199A (en) 1997-06-03 1999-08-10 International Business Machines Corporation User programmable interrupt mask with timeout for enhanced resource locking efficiency
US5875342A (en) 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6058472A (en) 1997-06-25 2000-05-02 Sun Microsystems, Inc. Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine
US5913049A (en) 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6463522B1 (en) 1997-12-16 2002-10-08 Intel Corporation Memory system for ordering load and store instructions in a processor that performs multithread execution
EP0942359B1 (de) 1998-02-19 2012-07-04 Lantiq Deutschland GmbH Vorrichtung zur Ausführung von Programmbefehlen
EP0942357A3 (de) 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Mit einer Mehrzahl von Befehlsformaten vereinbarer Datenprozessor
US6356270B2 (en) 1998-03-31 2002-03-12 Intel Corporation Efficient utilization of write-combining buffers
US6085312A (en) 1998-03-31 2000-07-04 Intel Corporation Method and apparatus for handling imprecise exceptions
US6014735A (en) * 1998-03-31 2000-01-11 Intel Corporation Instruction set extension using prefixes
US6581154B1 (en) 1999-02-17 2003-06-17 Intel Corporation Expanding microcode associated with full and partial width macroinstructions
US6405305B1 (en) 1999-09-10 2002-06-11 Advanced Micro Devices, Inc. Rapid execution of floating point load control word instructions
WO2001025900A1 (en) * 1999-10-06 2001-04-12 Cradle Technologies Risc processor using register codes for expanded instruction set
US6456891B1 (en) 1999-10-27 2002-09-24 Advanced Micro Devices, Inc. System and method for transparent handling of extended register states
JP3669884B2 (ja) 1999-11-11 2005-07-13 富士通株式会社 処理装置
US6560694B1 (en) * 2000-01-14 2003-05-06 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
US6779103B1 (en) 2000-09-29 2004-08-17 Intel Corporation Control word register renaming
JP2002175261A (ja) 2000-12-05 2002-06-21 Oki Electric Ind Co Ltd データ転送制御回路
US7529912B2 (en) 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7181596B2 (en) 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7328328B2 (en) 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US6823414B2 (en) 2002-03-01 2004-11-23 Intel Corporation Interrupt disabling apparatus, system, and method
US7395412B2 (en) 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7373483B2 (en) 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
TWI282066B (en) 2002-08-22 2007-06-01 Ip First Llc Apparatus and method for extending data modes in a microprocessor

Also Published As

Publication number Publication date
EP1359502A2 (de) 2003-11-05
EP1359502A3 (de) 2004-08-18
EP1359502B1 (de) 2008-12-03
US20030196077A1 (en) 2003-10-16
US7380109B2 (en) 2008-05-27

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