DE60332510D1 - Mikroprozessor und Verfahren zur selektiven Steuerung des Zurückschreibens von Bedingungscodes - Google Patents

Mikroprozessor und Verfahren zur selektiven Steuerung des Zurückschreibens von Bedingungscodes

Info

Publication number
DE60332510D1
DE60332510D1 DE60332510T DE60332510T DE60332510D1 DE 60332510 D1 DE60332510 D1 DE 60332510D1 DE 60332510 T DE60332510 T DE 60332510T DE 60332510 T DE60332510 T DE 60332510T DE 60332510 D1 DE60332510 D1 DE 60332510D1
Authority
DE
Germany
Prior art keywords
rewriting
microprocessor
selectively controlling
condition codes
codes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60332510T
Other languages
English (en)
Inventor
Glenn G Henry
Terry Parks
Rodney E Hooker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IP First LLC
Original Assignee
IP First LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=28044301&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60332510(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by IP First LLC filed Critical IP First LLC
Application granted granted Critical
Publication of DE60332510D1 publication Critical patent/DE60332510D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
DE60332510T 2002-04-02 2003-03-18 Mikroprozessor und Verfahren zur selektiven Steuerung des Zurückschreibens von Bedingungscodes Expired - Lifetime DE60332510D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36956702P 2002-04-02 2002-04-02
US10/144,593 US7185180B2 (en) 2002-04-02 2002-05-09 Apparatus and method for selective control of condition code write back

Publications (1)

Publication Number Publication Date
DE60332510D1 true DE60332510D1 (de) 2010-06-24

Family

ID=28044301

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60332510T Expired - Lifetime DE60332510D1 (de) 2002-04-02 2003-03-18 Mikroprozessor und Verfahren zur selektiven Steuerung des Zurückschreibens von Bedingungscodes

Country Status (3)

Country Link
US (1) US7185180B2 (de)
EP (1) EP1351135B1 (de)
DE (1) DE60332510D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
DE10358358B4 (de) * 2003-12-12 2008-05-08 Infineon Technologies Ag Mikroprozessoranordnung und Verfahren zum Betreiben einer Mikroprozessoranordnung
US8719837B2 (en) 2004-05-19 2014-05-06 Synopsys, Inc. Microprocessor architecture having extendible logic
US8212823B2 (en) 2005-09-28 2012-07-03 Synopsys, Inc. Systems and methods for accelerating sub-pixel interpolation in video processing applications
JP5193624B2 (ja) 2008-02-19 2013-05-08 ルネサスエレクトロニクス株式会社 データプロセッサ
US8504807B2 (en) 2009-12-26 2013-08-06 Intel Corporation Rotate instructions that complete execution without reading carry flag
US11080045B2 (en) * 2011-12-22 2021-08-03 Intel Corporation Addition instructions with independent carry chains
JP5610551B2 (ja) * 2013-02-04 2014-10-22 ルネサスエレクトロニクス株式会社 データプロセッサ
US9792121B2 (en) 2013-05-21 2017-10-17 Via Technologies, Inc. Microprocessor that fuses if-then instructions
JP5767374B2 (ja) * 2014-07-30 2015-08-19 ルネサスエレクトロニクス株式会社 データプロセッサ
US10394568B2 (en) 2015-09-30 2019-08-27 International Business Machines Corporation Exception handling for applications with prefix instructions
US10877759B2 (en) 2015-09-30 2020-12-29 International Business Machines Corporation Managing the capture of information in applications with prefix instructions
US9870305B2 (en) 2015-09-30 2018-01-16 International Business Machines Corporation Debugging of prefixed code
US10761852B2 (en) 2015-09-30 2020-09-01 International Business Machines Corporation Extending data range addressing
US20190196820A1 (en) * 2017-12-21 2019-06-27 Intel Corporation Apparatus and method for right shifting packed quadwords and extracting packed doublewords
US20190196821A1 (en) * 2017-12-21 2019-06-27 Intel Corporation Apparatus and method for right-shifting packed quadwords and extracting packed words

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US587342A (en) * 1897-08-03 Lubricated bullet
US3657705A (en) * 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
JPS57157362A (en) * 1981-03-25 1982-09-28 Hitachi Ltd Method and apparatus of execution path career data pickup for architecture program
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
JPS6491228A (en) * 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
US5218712A (en) * 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
US5303358A (en) 1990-01-26 1994-04-12 Apple Computer, Inc. Prefix instruction for modification of a subsequent instruction
JPH04306735A (ja) * 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
EP0550289A3 (en) 1992-01-02 1993-11-10 Amdahl Corp A mechanism to detect stores into the instruction stream
JP3644959B2 (ja) * 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
ZA954460B (en) * 1994-09-30 1996-02-05 Intel Corp Method and apparatus for processing memory-type information within a microprocessor
KR100374803B1 (ko) * 1995-05-25 2003-05-12 삼성전자주식회사 튜닝포크형자이로스코프
US5768574A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
WO1997022922A1 (en) 1995-12-15 1997-06-26 Intel Corporation Instruction encoding techniques for microcontroller architecture
US5826089A (en) * 1996-01-04 1998-10-20 Advanced Micro Devices, Inc. Instruction translation unit configured to translate from a first instruction set to a second instruction set
JP3663710B2 (ja) * 1996-01-17 2005-06-22 ヤマハ株式会社 プログラムの生成方法およびプロセッサの割込制御方法
US5857103A (en) * 1996-06-14 1999-01-05 Sun Microsystems, Inc. Method and apparatus for addressing extended registers on a processor in a computer system
US5778220A (en) * 1996-11-18 1998-07-07 Intel Corporation Method and apparatus for disabling interrupts in a highly pipelined processor
JPH10161871A (ja) * 1996-11-28 1998-06-19 Toshiba Corp プロセッサ
US5937199A (en) * 1997-06-03 1999-08-10 International Business Machines Corporation User programmable interrupt mask with timeout for enhanced resource locking efficiency
US5875342A (en) 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6058472A (en) * 1997-06-25 2000-05-02 Sun Microsystems, Inc. Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine
US6230259B1 (en) * 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
EP0942359B1 (de) 1998-02-19 2012-07-04 Lantiq Deutschland GmbH Vorrichtung zur Ausführung von Programmbefehlen
EP0942357A3 (de) * 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Mit einer Mehrzahl von Befehlsformaten vereinbarer Datenprozessor
US6356270B2 (en) 1998-03-31 2002-03-12 Intel Corporation Efficient utilization of write-combining buffers
US6085312A (en) * 1998-03-31 2000-07-04 Intel Corporation Method and apparatus for handling imprecise exceptions
US6014735A (en) 1998-03-31 2000-01-11 Intel Corporation Instruction set extension using prefixes
US6581154B1 (en) * 1999-02-17 2003-06-17 Intel Corporation Expanding microcode associated with full and partial width macroinstructions
WO2001025900A1 (en) * 1999-10-06 2001-04-12 Cradle Technologies Risc processor using register codes for expanded instruction set
US6456891B1 (en) * 1999-10-27 2002-09-24 Advanced Micro Devices, Inc. System and method for transparent handling of extended register states
JP3669884B2 (ja) * 1999-11-11 2005-07-13 富士通株式会社 処理装置
US6560694B1 (en) * 2000-01-14 2003-05-06 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
JP2002175261A (ja) * 2000-12-05 2002-06-21 Oki Electric Ind Co Ltd データ転送制御回路
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7315921B2 (en) * 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US6823414B2 (en) * 2002-03-01 2004-11-23 Intel Corporation Interrupt disabling apparatus, system, and method
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor

Also Published As

Publication number Publication date
US7185180B2 (en) 2007-02-27
EP1351135A2 (de) 2003-10-08
EP1351135B1 (de) 2010-05-12
EP1351135A3 (de) 2008-03-12
US20030188133A1 (en) 2003-10-02

Similar Documents

Publication Publication Date Title
DE60332510D1 (de) Mikroprozessor und Verfahren zur selektiven Steuerung des Zurückschreibens von Bedingungscodes
DE60214971D1 (de) Verfahren und Vorrichtung zur Steuerung von Geräten
DE602004032295D1 (de) Roboter und Verfahren zur Steuerung des Verhaltens desselben
DE60212925D1 (de) Kühlschrank und Verfahren zur Steuerung eines Kühlschranks
DE10139936B4 (de) Verfahren und Anordnung zur Steuerung von Datenpaketen
DE60212744D1 (de) Vorrichtung zur Steuerung der Spannungsversorgung und zugehöriges Verfahren
DE60204924D1 (de) System und Verfahren zur Steuerung von Heimgeräten
DE60317641D1 (de) Verfahren und system zur steuerung der bohrlochzirkulationsrate
DE60212114D1 (de) System und verfahren zur überwachung und steuerung
DE602005023693D1 (de) Verfahren und Vorrichtung zur Steuerung des Leistungsniveaus und/oder Kontrastes einer Anzeigevorrichtung
DE60031404D1 (de) Verfahren und vorrichtung zur dynamischen änderung der grössen von pools, die die leistungsaufnahme von speichern steuern
DE60309410D1 (de) Kondensationwäschetrockner und Verfahren zur Steuerung des Betriebs desselben
ATE415614T1 (de) System und verfahren zur steuerung von sprengarbeiten
DE60315228D1 (de) Einrichtung und verfahren zur rückkopplungskontrolle
DE10296974T5 (de) Mehrzweckfernsteuerung und Verfahren zum Steuern derselben
DE50309304D1 (de) Verfahren zur Bekämpfung von Gerüchen und/oder Schadstoffen im Fahrzeuginnenraum
DE60323590D1 (de) Kreuztischvorrichtung und Verfahren zur Steuerung derselben
DE60302809D1 (de) Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute
DE60316292D1 (de) Reinigungsmittel zur steuerung und entfernung von allergenen
DE60311222D1 (de) Vorrichtung zur Durchführung einer Gesamtflüssigkeitsventilation mit Kontrolle von Restvolumen und Beatmungszyklusprofil
DE50312128D1 (de) Lenkung und Verfahren zur Lenkung
DE60318288D1 (de) Wiedergabegerät, Ausgabegerät und Verfahren zur Steuerung des Leistungsverbrauchs
DE112004002631D2 (de) Verfahren und Vorrichtung zur Anpassung von Funktionen zur Steuerung von Betriebsabläufen
DE50213474D1 (de) Verfahren zur steuerung und regelung eines antriebsstranges
DE50206035D1 (de) Verfahren und anordnung zur ansteuerung von rückhaltemitteln

Legal Events

Date Code Title Description
8364 No opposition during term of opposition