DE63811T1 - Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer. - Google Patents
Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer.Info
- Publication number
- DE63811T1 DE63811T1 DE198282103521T DE82103521T DE63811T1 DE 63811 T1 DE63811 T1 DE 63811T1 DE 198282103521 T DE198282103521 T DE 198282103521T DE 82103521 T DE82103521 T DE 82103521T DE 63811 T1 DE63811 T1 DE 63811T1
- Authority
- DE
- Germany
- Prior art keywords
- substrate carrier
- strips
- sectional areas
- parts
- connecting band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12188—All metal or with adjacent metals having marginal feature for indexing or weakened portion for severing
- Y10T428/12194—For severing perpendicular to longitudinal dimension
Claims (15)
1. Verfahren zum Herstellen einer in Kunststoff vergossenen
Halbleitereinrichtung, dadurch gekennzeichnet, daß durch obere (13) und unter Formen (14) zumindest Außenanschlüsse
(6,10,11) und Streifen (15,16) einer Anordnung
für eine Halbleitereinrichtung (1) festgeklemmt werden, welche durch einen Anschlußrahmen gebildet ist, welche ein
erstes Verbindungsband (9), das mit den Anschlußleitungen (6,10,11) verbunden ist, die von einer Seite eines Substratträger (2) vorstehen, der auch als Wärmesenke verwendet
wird, und ein zweites Verbindungsband (17) aufweist, das mit den Streifen (15,16) verbunden ist, welche Teile mit
kleinen Querschnittsflächen und einer vorbestimmten Länge aufweisen, die von der anderen Seite des Substratträgers
(2) vorstehen, wobei die Querschnittsflächen senkrecht zu einer Erstreckungsrichtung der Streifen (15,16 ) verlaufen,
so daß der Substratträger (2). in einem durch die oberen und unteren Formen (13,14) gebildeten Hohlraum freigehalten ist,
und daß die Teile mit kleinen Querschnittsflächen zum Teil VIl/XX/Ktz " " - 2 -
«■(089)9882 72-74 Telex: 524 56OBERGd Bankkonten: Bayer. Vereinsbank München 453100 (BLZ 700 202 70)
Telegramme (cable): Telekopierer: (089) 983049 Hypo-Bank München 4410122 850 (BLZ 700 20011) Swift Code: HYPO DE
BERGSTAPFPATENT München KaIIe Intotec 6350 Gr. Il+ Ml Postscheck München 653 43-808 (BLZ 700100 80)
in dem Hohlraum angeordnet sein können und deren übrige Teile zwischen den oberen und unteren Formen (13,14) angeordnet
sind, daß Kunststoff in den Hohlraum gespritzt wird, und daß dann die Teile der Streifen (15,16) mit den kleinen
Querschnittsflächen, die aus dem vergossenen Kunststoffgehäuse
vorstehen, durchschnitten werden und ein Verbindungsteil zwischen den Außenanschlüssen (6,10,11) und dem ersten
Verbindungsband (9) durchschnitten wird.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet,
daß die Teile mit kleinen Querschnittsflächen gebogen und durch einen Sprödbruch durchschnitten
werden, indem beim Durchtrennen der Teile der Streifen (15,16) mit den kleinen Querschnittsflächen, welche von
dem vergossenen Kunststoffgehäuse nach außen vorstehen, eine Biegebeanspruchung auf das zweite Verbindungsband
(17), durch das die Streifen (15,16) verbunden sind, entlang der Endfläche des vergossenen Gehäuses ausgeübt wird.
3. Verfahren nach Anspruch 1, dadurch gekennzeichnet,
daß der durch die oberen und unteren Formen (13,16) gebildete Hohlraum aus einem ersten und
einem zweiten Teil besteht, wobei ein Abstand zwischen einer Ober- und einer Unterseite des ersten Teils größer
als der Abstand in dem zweiten Teil ist, um so ein Halbleiterelement-Halterungsteil
der Anordnung für die Halbleitereinrichtung in dem ersten Teil an einer vorgegebenen
Stelle anzuordnen.
^O
4. Verfahren nach Anspruch 1, dadurch g e k e η nz
e i c h η e t, daß der durch die oberen und unteren Formen (13,14) gebildete Hohlraum aus einem ersten und
einem zweiten Teil besteht, wobei ein Abstand zwischen einer Oberseite und einer Unterseite des ersten Teils
größer als der Abstand in dem zweiten Teil ist, und ein Formansatz zum Ausbilden einer durchgehenden Bohrung, um
die Halbleitereinrichtung (1) an dem Substratträger (2)
mit Hilfe einer Schraube zu haltern, in dem zweiten Teil ausgebildet ist.
5. Verfahren nach Anspruch 1, dadurch gekennzeich-5.
η e t, daß die Dicke des Kunststoffes, der unter dem Substratträger
(2) vergossen ist, in einem Bereich von 0,3 bis 0,5 mm liegt.
6. Anschlußrahmen, gekenn ζ e ichnet durch
ein erstes Verbindungsband (9) durch eine Anzahl Anschlußleitungen
(6,10,11), die in einer Richtung von dem ersten Verbindungsband (9) aus verlaufen, durch einen Substratträger (2), welcher auch als Wärmesenke dient, die mit
einer Oberseite eineir der Anschlußleitungen (6,10,11) verbunden
ist, durch Streifen (15,16), welche Teile mit kleinen Querschnittsflächen und einer vorbestimmten Länge
haben, wobei die Querschnitte senkrecht zu einer Erstrekkungsrichtung der Streifen (15,16) sind, und deren Enden
mit einer Seite des Substratträgers (2) verbunden sind, die der anderen Seite gegenüberliegt, die mit den Anschlußleitungen
(6,10,11) verbunden ist, und durch ein zweites Verbindungsband
(17), das parallel zu dem ersten Verbindungsband (9) verläuft, wobei dazwischen der Substratträger (2)
angeordnet ist, und wobei die Streifen (15,16) eine geringere
Dicke als der Substratträger (2) haben, so daß die Streifen (15,16) dünner als der Substratträger (2) sind
und die Rückseiten der Streifen (15,16) auf einem höheren Niveau liegen als eine Rückseite des Substratträgers (2).
7. Anschlußrahmen nach Anspruch 6, dadurch gekennzeichnet,
daß die Anzahl Streifen (15,16), deren
Enden mit einem Ende des Substratträgers (2) verbunden
sind, dessen anderes Ende mit der äußeren Anschlußleitung
(6,10,11) verbunden ist, zwei ist.
35
35
8. Anschlußrahmen nach Anspruch 6, dadurch g e k e η nz e i c h η et, daß die Streifen (15,16), die mit einem
Ende des Substratträgers (2) verbunden sind, dessen_anderes
0063611
Ende mit der Anschlußleitung (6) verbunden ist, schmalere Teile aufweisen, um dadurch die Querschnittsflächen von
Teilen der Streifen (15,16) zu verringern.
9. Anschlußrahmen nach Anspruch 6, dadurch gekennzeichnet,
daß die Streifen (15,16), die mit einem
Ende des Substratträger (2) verbunden sind, dessen anderes
Ende mit der Anschlußleitung (6) verbunden ist, Öffnungen aufweisen, um die Querschnittsflächen von Teilen der Strei-
IQ fen (15,16) wesentlich zu verkleinern.
10. Anschlußrahmen nach Anspruch 6, dadurch gekennzeichnet,
daß eine Anzahl öffnungen (8,20) in jeder der beiden Verbindungsbänder (9,20) in gleichen'Abständen
voneinander ausgebildet sind.
11. Anschlußrahmen, gekennzeichnet durch einen Substratträger(2) , welcher ein Halbleitersubstrat
(1) trägt, das mit einer Oberseite einer einer Anzahl von Anschlußleitungen (6,10,11) verbunden ist, die sich von
einem Verbindungsband (9) aus in der gleichen Richtung erstrecken,
wobei ein dreidimensionales Muster in Form von Rillen oder Bohrungen auf zumindest einem Teil einer Oberfläche
des Substratträgers (2) ausgebildet ist, dessen andere Oberfläche das Halbleitersubstrat (1) trägt.
12. Anschlußrahmen nach Anspruch 11, dadurch gekennzeichnet,
daß das dreidimsionale Muster Rillen (27) aufweist, die senkrecht zu einer Längsrichtung des Substratträgers
(2) verlaufen.
13. Anschlußrahmen nach Anspruch 11, dadurch gekennzeichnet,
daß das dreidimensionale Muster Rillen (27) in Gitterform aufweist.
14. Anschlußrahmen nach Anspruch 11,dadurch gekennzeichnet,
daß das dreidimensionale Muster Rillen
C
(27) aufweist, die parallel zu einer Längsrichtung des Substratträgers (2) verlaufen.
15. Anschlußrahmen nach Anspruch 11, dadurch g e k e η nzeichnet,
daß das dreidimensionale Muster eine Anzahl Bohrungen (28) aufweist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6489381A JPS57178352A (en) | 1981-04-28 | 1981-04-28 | Manufacture of resin sealing type semiconductor device and lead frame employed thereon |
JP6430781A JPS5710325A (en) | 1980-05-16 | 1981-04-30 | Device for simultaneously and continuously supplying powdered solid or liquid into treating machine |
Publications (1)
Publication Number | Publication Date |
---|---|
DE63811T1 true DE63811T1 (de) | 1983-04-28 |
Family
ID=26405427
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE198282103521T Pending DE63811T1 (de) | 1981-04-28 | 1982-04-26 | Verfahren zum herstellen einer in kunststoff verkapselten halbleiteranordnung und ein leitergitter dafuer. |
DE8282103521T Expired DE3270561D1 (en) | 1981-04-28 | 1982-04-26 | A method for manufacturing a plastic encapsulated semiconductor device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282103521T Expired DE3270561D1 (en) | 1981-04-28 | 1982-04-26 | A method for manufacturing a plastic encapsulated semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (2) | US4451973A (de) |
EP (1) | EP0063811B1 (de) |
CA (1) | CA1200623A (de) |
DE (2) | DE63811T1 (de) |
Families Citing this family (84)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57147260A (en) * | 1981-03-05 | 1982-09-11 | Matsushita Electronics Corp | Manufacture of resin-sealed semiconductor device and lead frame used therefor |
US4641418A (en) * | 1982-08-30 | 1987-02-10 | International Rectifier Corporation | Molding process for semiconductor devices and lead frame structure therefor |
JPS59130449A (ja) * | 1983-01-17 | 1984-07-27 | Nec Corp | 絶縁型半導体素子用リードフレーム |
JPS59135753A (ja) * | 1983-01-25 | 1984-08-04 | Toshiba Corp | 半導体装置とその製造方法 |
IT1212780B (it) * | 1983-10-21 | 1989-11-30 | Ates Componenti Elettron | Contenitore in metallo e resina per dispositivo a semiconduttore adatto al fissaggio su un dissipatore non perfettamente piano e processo per la sua fabbricazione. |
JPS60186044A (ja) * | 1983-12-12 | 1985-09-21 | テキサス インスツルメンツ インコ−ポレイテツド | 集積回路装置 |
JPS60128646A (ja) * | 1983-12-16 | 1985-07-09 | Hitachi Ltd | 絶縁型パワートランジスタの製造方法 |
IT1213139B (it) * | 1984-02-17 | 1989-12-14 | Ates Componenti Elettron | Componente elettronico integrato di tipo "single-in-line" eprocedimento per la sua fabbricazione. |
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-
1982
- 1982-04-13 US US06/367,809 patent/US4451973A/en not_active Expired - Lifetime
- 1982-04-26 EP EP19820103521 patent/EP0063811B1/de not_active Expired
- 1982-04-26 DE DE198282103521T patent/DE63811T1/de active Pending
- 1982-04-26 DE DE8282103521T patent/DE3270561D1/de not_active Expired
- 1982-04-27 CA CA000401752A patent/CA1200623A/en not_active Expired
-
1984
- 1984-02-17 US US06/581,251 patent/US4589010A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE3270561D1 (en) | 1986-05-22 |
EP0063811A1 (de) | 1982-11-03 |
EP0063811B1 (de) | 1986-04-16 |
CA1200623A (en) | 1986-02-11 |
US4589010A (en) | 1986-05-13 |
US4451973A (en) | 1984-06-05 |
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