DE68902317D1 - Multiport-speicher. - Google Patents
Multiport-speicher.Info
- Publication number
- DE68902317D1 DE68902317D1 DE8989100100T DE68902317T DE68902317D1 DE 68902317 D1 DE68902317 D1 DE 68902317D1 DE 8989100100 T DE8989100100 T DE 8989100100T DE 68902317 T DE68902317 T DE 68902317T DE 68902317 D1 DE68902317 D1 DE 68902317D1
- Authority
- DE
- Germany
- Prior art keywords
- multiport storage
- multiport
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63008929A JPH07107792B2 (ja) | 1988-01-19 | 1988-01-19 | マルチポートメモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68902317D1 true DE68902317D1 (de) | 1992-09-10 |
DE68902317T2 DE68902317T2 (de) | 1993-01-07 |
Family
ID=11706350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8989100100T Expired - Lifetime DE68902317T2 (de) | 1988-01-19 | 1989-01-04 | Multiport-speicher. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5007028A (de) |
EP (1) | EP0325105B1 (de) |
JP (1) | JPH07107792B2 (de) |
KR (1) | KR930007281B1 (de) |
DE (1) | DE68902317T2 (de) |
MY (1) | MY103962A (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04125892A (ja) * | 1990-09-06 | 1992-04-27 | Samsung Electron Co Ltd | ジュアルポートメモリ素子におけるチップエネイブル信号制御回路 |
JPH04153979A (ja) * | 1990-10-15 | 1992-05-27 | Mitsubishi Electric Corp | 半導体装置 |
JP2596208B2 (ja) * | 1990-10-19 | 1997-04-02 | 日本電気株式会社 | メモリ装置 |
KR960004735B1 (ko) * | 1991-03-19 | 1996-04-12 | 후지쓰 가부시끼가이샤 | 멀티포트 메모리(Multiport Memory) |
US5394172A (en) * | 1993-03-11 | 1995-02-28 | Micron Semiconductor, Inc. | VRAM having isolated array sections for providing write functions that will not affect other array sections |
US5502683A (en) * | 1993-04-20 | 1996-03-26 | International Business Machines Corporation | Dual ported memory with word line access control |
US5719890A (en) * | 1995-06-01 | 1998-02-17 | Micron Technology, Inc. | Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM |
US6209071B1 (en) | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
US6487207B1 (en) | 1997-02-26 | 2002-11-26 | Micron Technology, Inc. | Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology |
WO1999019874A1 (en) | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Power control system for synchronous memory device |
KR100558552B1 (ko) | 2003-12-30 | 2006-03-10 | 삼성전자주식회사 | 반도체 메모리장치의 데이터 억세스회로 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633411A (en) * | 1982-12-27 | 1986-12-30 | Rockwell International Corporation | Link quality analyzer |
US4535428A (en) * | 1983-03-10 | 1985-08-13 | International Business Machines Corporation | Multi-port register implementations |
US4720819A (en) * | 1983-12-30 | 1988-01-19 | Texas Instruments Incorporated | Method and apparatus for clearing the memory of a video computer |
JPS61160898A (ja) * | 1985-01-05 | 1986-07-21 | Fujitsu Ltd | 半導体記憶装置 |
JPS6289149A (ja) * | 1985-10-15 | 1987-04-23 | Agency Of Ind Science & Technol | 多ポ−トメモリシステム |
JPS62287497A (ja) * | 1986-06-06 | 1987-12-14 | Fujitsu Ltd | 半導体記憶装置 |
-
1988
- 1988-01-19 JP JP63008929A patent/JPH07107792B2/ja not_active Expired - Lifetime
-
1989
- 1989-01-03 MY MYPI89000002A patent/MY103962A/en unknown
- 1989-01-04 EP EP89100100A patent/EP0325105B1/de not_active Expired - Lifetime
- 1989-01-04 DE DE8989100100T patent/DE68902317T2/de not_active Expired - Lifetime
- 1989-01-19 KR KR1019890000529A patent/KR930007281B1/ko not_active IP Right Cessation
-
1990
- 1990-07-16 US US07/552,851 patent/US5007028A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR890012315A (ko) | 1989-08-25 |
JPH01184788A (ja) | 1989-07-24 |
EP0325105A1 (de) | 1989-07-26 |
EP0325105B1 (de) | 1992-08-05 |
MY103962A (en) | 1993-10-30 |
US5007028A (en) | 1991-04-09 |
JPH07107792B2 (ja) | 1995-11-15 |
DE68902317T2 (de) | 1993-01-07 |
KR930007281B1 (ko) | 1993-08-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP T |