DE68918066D1 - Dreidimensionale gestapelte LSI. - Google Patents

Dreidimensionale gestapelte LSI.

Info

Publication number
DE68918066D1
DE68918066D1 DE68918066T DE68918066T DE68918066D1 DE 68918066 D1 DE68918066 D1 DE 68918066D1 DE 68918066 T DE68918066 T DE 68918066T DE 68918066 T DE68918066 T DE 68918066T DE 68918066 D1 DE68918066 D1 DE 68918066D1
Authority
DE
Germany
Prior art keywords
dimensional stacked
stacked lsi
lsi
dimensional
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918066T
Other languages
English (en)
Other versions
DE68918066T2 (de
DE68918066T3 (de
Inventor
Yasuhiro Tomita
Yoshiyuki Takagi
Shigenobu Akiyama
Kenichi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Energy and Industrial Technology Development Organization
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18189378&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68918066(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE68918066D1 publication Critical patent/DE68918066D1/de
Publication of DE68918066T2 publication Critical patent/DE68918066T2/de
Application granted granted Critical
Publication of DE68918066T3 publication Critical patent/DE68918066T3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5286Arrangements of power or ground buses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE68918066T 1988-12-23 1989-12-23 Dreidimensionale gestapelte LSI. Expired - Fee Related DE68918066T3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32657888 1988-12-23

Publications (3)

Publication Number Publication Date
DE68918066D1 true DE68918066D1 (de) 1994-10-13
DE68918066T2 DE68918066T2 (de) 1995-04-27
DE68918066T3 DE68918066T3 (de) 1998-03-05

Family

ID=18189378

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918066T Expired - Fee Related DE68918066T3 (de) 1988-12-23 1989-12-23 Dreidimensionale gestapelte LSI.

Country Status (3)

Country Link
US (1) US5191405A (de)
EP (1) EP0374971B2 (de)
DE (1) DE68918066T3 (de)

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US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
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US6841813B2 (en) * 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
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US6843421B2 (en) 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6815781B2 (en) 2001-09-25 2004-11-09 Matrix Semiconductor, Inc. Inverted staggered thin film transistor with salicided source/drain structures and method of making same
US6624485B2 (en) 2001-11-05 2003-09-23 Matrix Semiconductor, Inc. Three-dimensional, mask-programmed read only memory
US7018878B2 (en) * 2001-11-07 2006-03-28 Matrix Semiconductor, Inc. Metal structures for integrated circuits and methods for making the same
DE10200399B4 (de) * 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6731011B2 (en) * 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
US6853049B2 (en) * 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6728023B1 (en) 2002-05-28 2004-04-27 Silicon Light Machines Optical device arrays with optimized image resolution
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6829258B1 (en) 2002-06-26 2004-12-07 Silicon Light Machines, Inc. Rapidly tunable external cavity laser
US6737675B2 (en) 2002-06-27 2004-05-18 Matrix Semiconductor, Inc. High density 3D rail stack arrays
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6714337B1 (en) 2002-06-28 2004-03-30 Silicon Light Machines Method and device for modulating a light beam and having an improved gamma response
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
JP3908147B2 (ja) * 2002-10-28 2007-04-25 シャープ株式会社 積層型半導体装置及びその製造方法
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
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US7245021B2 (en) * 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
JP5354765B2 (ja) * 2004-08-20 2013-11-27 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置の製造方法
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Also Published As

Publication number Publication date
DE68918066T2 (de) 1995-04-27
EP0374971B2 (de) 1997-08-06
DE68918066T3 (de) 1998-03-05
US5191405A (en) 1993-03-02
EP0374971B1 (de) 1994-09-07
EP0374971A2 (de) 1990-06-27
EP0374971A3 (en) 1990-09-19

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Owner name: NEW ENERGY AND INDUSTRIAL TECHNOLOGY DEVELOPMENT O

8339 Ceased/non-payment of the annual fee