DE68923311D1 - Verfahren zur Herstellung eines Feld-Effekt-Transistors. - Google Patents

Verfahren zur Herstellung eines Feld-Effekt-Transistors.

Info

Publication number
DE68923311D1
DE68923311D1 DE68923311T DE68923311T DE68923311D1 DE 68923311 D1 DE68923311 D1 DE 68923311D1 DE 68923311 T DE68923311 T DE 68923311T DE 68923311 T DE68923311 T DE 68923311T DE 68923311 D1 DE68923311 D1 DE 68923311D1
Authority
DE
Germany
Prior art keywords
manufacturing
field
effect transistor
transistor
effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923311T
Other languages
English (en)
Other versions
DE68923311T2 (de
Inventor
Sin-Ichi C O Yokohama Shikata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Publication of DE68923311D1 publication Critical patent/DE68923311D1/de
Application granted granted Critical
Publication of DE68923311T2 publication Critical patent/DE68923311T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Formation Of Insulating Films (AREA)
DE68923311T 1988-04-11 1989-04-06 Verfahren zur Herstellung eines Feld-Effekt-Transistors. Expired - Fee Related DE68923311T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63088759A JP2685149B2 (ja) 1988-04-11 1988-04-11 電界効果トランジスタの製造方法

Publications (2)

Publication Number Publication Date
DE68923311D1 true DE68923311D1 (de) 1995-08-10
DE68923311T2 DE68923311T2 (de) 1996-04-04

Family

ID=13951809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923311T Expired - Fee Related DE68923311T2 (de) 1988-04-11 1989-04-06 Verfahren zur Herstellung eines Feld-Effekt-Transistors.

Country Status (4)

Country Link
US (1) US4962054A (de)
EP (1) EP0337299B1 (de)
JP (1) JP2685149B2 (de)
DE (1) DE68923311T2 (de)

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US5138406A (en) * 1989-04-04 1992-08-11 Eaton Corporation Ion implantation masking method and devices
US5250453A (en) * 1989-04-12 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Production method of a semiconductor device
JPH02271537A (ja) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2553699B2 (ja) * 1989-04-12 1996-11-13 三菱電機株式会社 半導体装置の製造方法
JP2786307B2 (ja) * 1990-04-19 1998-08-13 三菱電機株式会社 電界効果トランジスタ及びその製造方法
DE4143616C2 (de) * 1990-05-02 1998-09-17 Mitsubishi Electric Corp Verfahren zur Herstellung einer Halbleitereinrichtung
EP0501275A3 (en) * 1991-03-01 1992-11-19 Motorola, Inc. Method of making symmetrical and asymmetrical mesfets
KR960012587B1 (ko) * 1991-10-01 1996-09-23 니뽄 덴끼 가부시끼가이샤 비대칭적으로 얇게 도핑된 드레인-금속 산화물 반도체 전계효과 트랜지스터(ldd-mosfet) 제조 방법
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
KR950013790B1 (ko) * 1992-12-02 1995-11-16 현대전자산업주식회사 트렌치 구조를 이용한 불균일 도우핑 채널을 갖는 모스 트랜지스터(mosfet) 및 그 제조 방법
US5448085A (en) * 1993-04-05 1995-09-05 The United States Of America As Represented By The Secretary Of The Air Force Limited current density field effect transistor with buried source and drain
JP2606581B2 (ja) * 1994-05-18 1997-05-07 日本電気株式会社 電界効果トランジスタ及びその製造方法
JP3298601B2 (ja) * 1994-09-14 2002-07-02 住友電気工業株式会社 電界効果トランジスタおよびその製造方法
DE19621855C2 (de) * 1996-05-31 2003-03-27 Univ Dresden Tech Verfahren zur Herstellung von Metallisierungen auf Halbleiterkörpern unter Verwendung eines gepulsten Vakuumbogenverdampfers
US5909622A (en) * 1996-10-01 1999-06-01 Advanced Micro Devices, Inc. Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant
US5783458A (en) * 1996-10-01 1998-07-21 Advanced Micro Devices, Inc. Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US5893739A (en) * 1996-10-01 1999-04-13 Advanced Micro Devices, Inc. Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer
US5930592A (en) * 1996-10-01 1999-07-27 Advanced Micro Devices, Inc. Asymmetrical n-channel transistor having LDD implant only in the drain region
US5963809A (en) * 1997-06-26 1999-10-05 Advanced Micro Devices, Inc. Asymmetrical MOSFET with gate pattern after source/drain formation
WO2000003566A1 (fr) * 1998-07-13 2000-01-20 Toshiyuki Takamatsu Appareil a decharge pour micro-ondes
US6200843B1 (en) 1998-09-24 2001-03-13 International Business Machines Corporation High-voltage, high performance FETs
US6458666B2 (en) * 2000-06-09 2002-10-01 Texas Instruments Incorporated Spot-implant method for MOS transistor applications
US6750150B2 (en) * 2001-10-18 2004-06-15 Macronix International Co., Ltd. Method for reducing dimensions between patterns on a photoresist
KR100442780B1 (ko) * 2001-12-24 2004-08-04 동부전자 주식회사 반도체 소자의 트랜지스터 제조 방법
JP4302952B2 (ja) * 2002-08-30 2009-07-29 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US7279386B2 (en) * 2004-12-03 2007-10-09 Advanced Micro Devices, Inc. Method for forming a semiconductor arrangement with gate sidewall spacers of specific dimensions
US7670905B2 (en) * 2007-09-07 2010-03-02 Micron Technology, Inc. Semiconductor processing methods, and methods of forming flash memory structures
US7910995B2 (en) * 2008-04-24 2011-03-22 Fairchild Semiconductor Corporation Structure and method for semiconductor power devices
US20120309182A1 (en) * 2011-05-31 2012-12-06 Globalfoundries Inc. Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process
US10134859B1 (en) 2017-11-09 2018-11-20 International Business Machines Corporation Transistor with asymmetric spacers
US10249755B1 (en) 2018-06-22 2019-04-02 International Business Machines Corporation Transistor with asymmetric source/drain overlap
US10236364B1 (en) 2018-06-22 2019-03-19 International Busines Machines Corporation Tunnel transistor
US11621340B2 (en) * 2019-11-12 2023-04-04 International Business Machines Corporation Field-effect transistor structure and fabrication method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59124172A (ja) * 1982-12-30 1984-07-18 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Ｆｅｔ製造方法
JPS6046074A (ja) * 1983-08-24 1985-03-12 Toshiba Corp 電界効果トランジスタの製造方法
JPS60137070A (ja) * 1983-12-26 1985-07-20 Toshiba Corp 半導体装置の製造方法
JPS60143674A (ja) * 1983-12-29 1985-07-29 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPS6182482A (ja) * 1984-09-29 1986-04-26 Toshiba Corp ＧａＡｓ電界効果トランジスタの製造方法
JPS61181169A (ja) * 1985-02-06 1986-08-13 Matsushita Electric Ind Co Ltd 電界効果トランジスタの製造方法
JPS6229175A (ja) * 1985-07-29 1987-02-07 Nippon Telegr & Teleph Corp <Ntt> 電界効果型トランジスタの製造方法
JPH0815158B2 (ja) * 1985-09-04 1996-02-14 株式会社日立製作所 ショットキーゲート電界効果トランジスタの製造方法
JPS6272175A (ja) * 1985-09-26 1987-04-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4722909A (en) * 1985-09-26 1988-02-02 Motorola, Inc. Removable sidewall spacer for lightly doped drain formation using two mask levels
JPS62114275A (ja) * 1985-11-13 1987-05-26 Sharp Corp 自己整合型電界効果トランジスタ及びその製造方法
DE3576610D1 (de) * 1985-12-06 1990-04-19 Ibm Verfahren zum herstellen eines voellig selbstjustierten feldeffekttransistors.
JPS62166571A (ja) * 1986-01-20 1987-07-23 Fujitsu Ltd 半導体装置の製造方法
US4745082A (en) * 1986-06-12 1988-05-17 Ford Microelectronics, Inc. Method of making a self-aligned MESFET using a substitutional gate with side walls
JPH07120675B2 (ja) * 1986-08-13 1995-12-20 株式会社日立製作所 半導体装置製造方法
DE3751219T2 (de) * 1986-11-20 1995-08-03 Sumitomo Electric Industries Verfahren zur Herstellung eines Schottky-Barriere- Feldeffekttransistors.
JPS644275A (en) * 1987-06-26 1989-01-09 Nissha Printing Coating film forming device
US4753898A (en) * 1987-07-09 1988-06-28 Motorola, Inc. LDD CMOS process
JPS6428870A (en) * 1987-07-23 1989-01-31 Matsushita Electric Ind Co Ltd Manufacture of field-effect transistor

Also Published As

Publication number Publication date
EP0337299A2 (de) 1989-10-18
US4962054A (en) 1990-10-09
EP0337299B1 (de) 1995-07-05
JP2685149B2 (ja) 1997-12-03
JPH01259568A (ja) 1989-10-17
EP0337299A3 (en) 1990-11-14
DE68923311T2 (de) 1996-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee