DE68923490D1 - Prüfpunkt-Wiederholungssystem. - Google Patents

Prüfpunkt-Wiederholungssystem.

Info

Publication number
DE68923490D1
DE68923490D1 DE68923490T DE68923490T DE68923490D1 DE 68923490 D1 DE68923490 D1 DE 68923490D1 DE 68923490 T DE68923490 T DE 68923490T DE 68923490 T DE68923490 T DE 68923490T DE 68923490 D1 DE68923490 D1 DE 68923490D1
Authority
DE
Germany
Prior art keywords
checkpoint
repeat system
repeat
checkpoint repeat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923490T
Other languages
English (en)
Other versions
DE68923490T2 (de
Inventor
Barbara Ann Hall
Kevin Chuang-Chi Huang
John David Jabusch
Agnes Yee Ngai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68923490D1 publication Critical patent/DE68923490D1/de
Publication of DE68923490T2 publication Critical patent/DE68923490T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
DE68923490T 1988-06-30 1989-05-17 Prüfpunkt-Wiederholungssystem. Expired - Fee Related DE68923490T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21353588A 1988-06-30 1988-06-30

Publications (2)

Publication Number Publication Date
DE68923490D1 true DE68923490D1 (de) 1995-08-24
DE68923490T2 DE68923490T2 (de) 1996-03-07

Family

ID=22795477

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923490T Expired - Fee Related DE68923490T2 (de) 1988-06-30 1989-05-17 Prüfpunkt-Wiederholungssystem.

Country Status (4)

Country Link
US (1) US5418916A (de)
EP (1) EP0348652B1 (de)
JP (1) JPH0752399B2 (de)
DE (1) DE68923490T2 (de)

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US5845329A (en) * 1993-01-29 1998-12-01 Sanyo Electric Co., Ltd. Parallel computer
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US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
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JP3020833B2 (ja) * 1995-06-19 2000-03-15 株式会社東芝 チェックポイント取得システム
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US5751939A (en) * 1995-11-29 1998-05-12 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory
US5675768A (en) * 1996-02-01 1997-10-07 Unisys Corporation Store software instrumentation package instruction
JPH09330237A (ja) 1996-06-07 1997-12-22 Toshiba Corp プロセス切り替え装置およびプロセス切り替え方法
JP2916420B2 (ja) * 1996-09-04 1999-07-05 株式会社東芝 チェックポイント処理加速装置およびデータ処理方法
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JP3836928B2 (ja) * 1997-02-26 2006-10-25 株式会社日立製作所 データベース処理方法
JPH10320274A (ja) * 1997-03-19 1998-12-04 Toshiba Corp キャッシュフラッシュ装置及び同装置を備えた計算機システム、記録媒体
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US6061762A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
US5961636A (en) * 1997-09-22 1999-10-05 International Business Machines Corporation Checkpoint table for selective instruction flushing in a speculative execution unit
US6055660A (en) * 1997-10-02 2000-04-25 International Business Machines Corporation Method for identifying SMP bus transfer errors
US6247118B1 (en) 1998-06-05 2001-06-12 Mcdonnell Douglas Corporation Systems and methods for transient error recovery in reduced instruction set computer processors via instruction retry
JP3804823B2 (ja) * 2001-07-03 2006-08-02 日本電気株式会社 障害回復機能を備えたキャッシュシステムとそのキャッシュ制御方法
US7237075B2 (en) * 2002-01-22 2007-06-26 Columbia Data Products, Inc. Persistent snapshot methods
US20030220929A1 (en) * 2002-01-22 2003-11-27 Columbia Data Products, Inc. Managing finite data storage utilizing preservation weights
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US7493513B2 (en) * 2003-04-29 2009-02-17 International Business Machines Corporation Automatically freezing functionality of a computing entity responsive to an error
US6973552B2 (en) * 2003-05-12 2005-12-06 International Business Machines Corporation System and method to handle page validation with out-of-order fetch
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7743223B2 (en) * 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US7421565B1 (en) * 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7519771B1 (en) 2003-08-18 2009-04-14 Cray Inc. System and method for processing memory instructions using a forced order queue
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7366873B1 (en) * 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7503048B1 (en) 2003-08-18 2009-03-10 Cray Incorporated Scheduling synchronization of programs running as streams on multiple processors
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US7543133B1 (en) 2003-08-18 2009-06-02 Cray Inc. Latency tolerant distributed shared memory multiprocessor computer
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7467325B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Processor instruction retry recovery
US20060184771A1 (en) * 2005-02-11 2006-08-17 International Business Machines Mini-refresh processor recovery as bug workaround method using existing recovery hardware
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7734949B2 (en) * 2006-03-30 2010-06-08 Alcatel Lucent Information error recovery apparatus and methods
US8112751B2 (en) * 2007-03-01 2012-02-07 Microsoft Corporation Executing tasks through multiple processors that process different portions of a replicable task
JP2008299501A (ja) * 2007-05-30 2008-12-11 Sanyo Electric Co Ltd プロセッサ
US8255635B2 (en) * 2008-02-01 2012-08-28 International Business Machines Corporation Claiming coherency ownership of a partial cache line of data
US8250307B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Sourcing differing amounts of prefetch data in response to data prefetch requests
US8266381B2 (en) * 2008-02-01 2012-09-11 International Business Machines Corporation Varying an amount of data retrieved from memory based upon an instruction hint
US8140771B2 (en) * 2008-02-01 2012-03-20 International Business Machines Corporation Partial cache line storage-modifying operation based upon a hint
US20090198910A1 (en) * 2008-02-01 2009-08-06 Arimilli Ravi K Data processing system, processor and method that support a touch of a partial cache line of data
US8108619B2 (en) * 2008-02-01 2012-01-31 International Business Machines Corporation Cache management for partial cache line operations
US8117401B2 (en) * 2008-02-01 2012-02-14 International Business Machines Corporation Interconnect operation indicating acceptability of partial data delivery
US8131951B2 (en) * 2008-05-30 2012-03-06 Freescale Semiconductor, Inc. Utilization of a store buffer for error recovery on a store allocation cache miss
US8117390B2 (en) * 2009-04-15 2012-02-14 International Business Machines Corporation Updating partial cache lines in a data processing system
US8140759B2 (en) * 2009-04-16 2012-03-20 International Business Machines Corporation Specifying an access hint for prefetching partial cache block data in a cache hierarchy
CN102521151A (zh) * 2011-11-28 2012-06-27 华为技术有限公司 数据缓存方法和装置
US9645936B1 (en) * 2014-03-26 2017-05-09 Marvell International Ltd. System and method for informing hardware to limit writing in a memory hierarchy
KR102312399B1 (ko) * 2015-09-07 2021-10-15 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법

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JPS503553A (de) * 1973-05-14 1975-01-14
US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
US4044337A (en) * 1975-12-23 1977-08-23 International Business Machines Corporation Instruction retry mechanism for a data processing system
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US4442487A (en) * 1981-12-31 1984-04-10 International Business Machines Corporation Three level memory hierarchy using write and share flags
US4493035A (en) * 1982-12-07 1985-01-08 Motorola, Inc. Data processor version validation
US4703481A (en) * 1985-08-16 1987-10-27 Hewlett-Packard Company Method and apparatus for fault recovery within a computing system
US4814971A (en) * 1985-09-11 1989-03-21 Texas Instruments Incorporated Virtual memory recovery system using persistent roots for selective garbage collection and sibling page timestamping for defining checkpoint state
US4740969A (en) * 1986-06-27 1988-04-26 Hewlett-Packard Company Method and apparatus for recovering from hardware faults

Also Published As

Publication number Publication date
JPH0227440A (ja) 1990-01-30
EP0348652A2 (de) 1990-01-03
EP0348652B1 (de) 1995-07-19
EP0348652A3 (de) 1991-05-08
DE68923490T2 (de) 1996-03-07
JPH0752399B2 (ja) 1995-06-05
US5418916A (en) 1995-05-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee