DE68924967D1 - Integrierte Halbleiterschaltungsanordnung, die aus einem Sytem von Standardzellen besteht. - Google Patents

Integrierte Halbleiterschaltungsanordnung, die aus einem Sytem von Standardzellen besteht.

Info

Publication number
DE68924967D1
DE68924967D1 DE68924967T DE68924967T DE68924967D1 DE 68924967 D1 DE68924967 D1 DE 68924967D1 DE 68924967 T DE68924967 T DE 68924967T DE 68924967 T DE68924967 T DE 68924967T DE 68924967 D1 DE68924967 D1 DE 68924967D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
standard cells
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924967T
Other languages
English (en)
Other versions
DE68924967T2 (de
Inventor
Makoto C O Intellectual P Noda
Kazuhiro C O Intellectual Suda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68924967D1 publication Critical patent/DE68924967D1/de
Publication of DE68924967T2 publication Critical patent/DE68924967T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE68924967T 1988-12-20 1989-12-19 Integrierte Halbleiterschaltungsanordnung, die aus einem Sytem von Standardzellen besteht. Expired - Fee Related DE68924967T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63321147A JPH0727968B2 (ja) 1988-12-20 1988-12-20 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE68924967D1 true DE68924967D1 (de) 1996-01-11
DE68924967T2 DE68924967T2 (de) 1996-05-15

Family

ID=18129327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924967T Expired - Fee Related DE68924967T2 (de) 1988-12-20 1989-12-19 Integrierte Halbleiterschaltungsanordnung, die aus einem Sytem von Standardzellen besteht.

Country Status (5)

Country Link
US (1) US5095352A (de)
EP (1) EP0374842B1 (de)
JP (1) JPH0727968B2 (de)
KR (1) KR930009024B1 (de)
DE (1) DE68924967T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3031966B2 (ja) * 1990-07-02 2000-04-10 株式会社東芝 集積回路装置
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
DE4135654A1 (de) * 1991-10-29 2003-03-27 Lockheed Corp Dichtgepackte Verbindungsstruktur, die eine Abstandshalterstruktur und einen Zwischenraum enthält
JP3052519B2 (ja) * 1992-01-14 2000-06-12 日本電気株式会社 集積回路の電源配線設計方法
JPH0722583A (ja) * 1992-12-15 1995-01-24 Internatl Business Mach Corp <Ibm> 多層回路装置
JP2826446B2 (ja) * 1992-12-18 1998-11-18 三菱電機株式会社 半導体集積回路装置及びその設計方法
US5723908A (en) * 1993-03-11 1998-03-03 Kabushiki Kaisha Toshiba Multilayer wiring structure
US5539227A (en) * 1993-11-24 1996-07-23 Mitsubishi Denki Kabushiki Kaisha Multi-layer wiring
US5497027A (en) * 1993-11-30 1996-03-05 At&T Global Information Solutions Company Multi-chip module packaging system
US5663677A (en) * 1995-03-30 1997-09-02 Lucent Technologies Inc. Integrated circuit multi-level interconnection technique
US5723883A (en) * 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US5894142A (en) * 1996-12-11 1999-04-13 Hewlett-Packard Company Routing for integrated circuits
US6229161B1 (en) 1998-06-05 2001-05-08 Stanford University Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
US6331733B1 (en) * 1999-08-10 2001-12-18 Easic Corporation Semiconductor device
US6625787B1 (en) 1999-08-13 2003-09-23 Xilinx, Inc. Method and apparatus for timing management in a converted design
US6308309B1 (en) * 1999-08-13 2001-10-23 Xilinx, Inc. Place-holding library elements for defining routing paths
US6574711B2 (en) 1999-12-27 2003-06-03 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
JP3390408B2 (ja) * 2000-05-29 2003-03-24 エヌイーシーマイクロシステム株式会社 半導体集積回路
US6396149B1 (en) * 2000-06-13 2002-05-28 Sun Microsystems, Inc. Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
US6502231B1 (en) * 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
US7161226B2 (en) * 2003-10-20 2007-01-09 Industrial Technology Research Institute Multi-layered complementary wire structure and manufacturing method thereof
JP2008103610A (ja) * 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体集積回路の配線構造およびその設計方法と設計装置
US20090166843A1 (en) 2007-12-27 2009-07-02 Infineon Technologies Ag Semiconductor device and method for manufacturing a semiconductor device
TWI376615B (en) * 2008-01-30 2012-11-11 Realtek Semiconductor Corp Power mesh managing method utilized in an integrated circuit
US8421205B2 (en) 2010-05-06 2013-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Power layout for integrated circuits
US9070552B1 (en) * 2014-05-01 2015-06-30 Qualcomm Incorporated Adaptive standard cell architecture and layout techniques for low area digital SoC
US9496174B2 (en) * 2014-07-24 2016-11-15 Qualcomm Incorporated Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion
US10658292B2 (en) * 2017-04-24 2020-05-19 Taiwan Semiconductor Manufacturing Company Limited Metal patterning for internal cell routing
US11347925B2 (en) * 2017-05-01 2022-05-31 Advanced Micro Devices, Inc. Power grid architecture and optimization with EUV lithography

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
JPS5837953A (ja) * 1981-08-31 1983-03-05 Toshiba Corp 積層半導体集積回路装置
JPS5890740A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 半導体装置
JPS59111344A (ja) * 1982-12-17 1984-06-27 Nippon Telegr & Teleph Corp <Ntt> 多層配線構造
JPS61156751A (ja) * 1984-12-28 1986-07-16 Fujitsu Ltd 半導体集積回路
EP0177336B1 (de) * 1984-10-03 1992-07-22 Fujitsu Limited Integrierte Gate-Matrixstruktur

Also Published As

Publication number Publication date
KR930009024B1 (ko) 1993-09-18
EP0374842A3 (en) 1990-08-01
JPH0727968B2 (ja) 1995-03-29
KR900010998A (ko) 1990-07-11
EP0374842B1 (de) 1995-11-29
EP0374842A2 (de) 1990-06-27
DE68924967T2 (de) 1996-05-15
JPH02165652A (ja) 1990-06-26
US5095352A (en) 1992-03-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee