DE69015868D1 - Herstellungsverfahren einer logischen Halbleiterschaltung mit nichtflüchtigem Speicher. - Google Patents
Herstellungsverfahren einer logischen Halbleiterschaltung mit nichtflüchtigem Speicher.Info
- Publication number
- DE69015868D1 DE69015868D1 DE69015868T DE69015868T DE69015868D1 DE 69015868 D1 DE69015868 D1 DE 69015868D1 DE 69015868 T DE69015868 T DE 69015868T DE 69015868 T DE69015868 T DE 69015868T DE 69015868 D1 DE69015868 D1 DE 69015868D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- volatile memory
- logic circuit
- semiconductor logic
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1110505A JP2509697B2 (ja) | 1989-04-28 | 1989-04-28 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69015868D1 true DE69015868D1 (de) | 1995-02-23 |
DE69015868T2 DE69015868T2 (de) | 1995-06-22 |
Family
ID=14537474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69015868T Expired - Fee Related DE69015868T2 (de) | 1989-04-28 | 1990-04-27 | Herstellungsverfahren einer logischen Halbleiterschaltung mit nichtflüchtigem Speicher. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5158902A (de) |
EP (1) | EP0395084B1 (de) |
JP (1) | JP2509697B2 (de) |
KR (1) | KR930002295B1 (de) |
DE (1) | DE69015868T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2952887B2 (ja) * | 1989-05-20 | 1999-09-27 | 富士通株式会社 | 半導体装置およびその製造方法 |
KR100199258B1 (ko) * | 1990-02-09 | 1999-06-15 | 가나이 쓰도무 | 반도체집적회로장치 |
KR930007527B1 (ko) * | 1990-09-22 | 1993-08-12 | 삼성전자 주식회사 | 스토리지 셀 어레이와 주변회로를 갖는 불휘발성 반도체 메모리 장치의 제조방법 및 그 구조 |
JP2573432B2 (ja) * | 1991-02-18 | 1997-01-22 | 株式会社東芝 | 半導体集積回路の製造方法 |
JP3049100B2 (ja) * | 1991-03-04 | 2000-06-05 | 富士通株式会社 | 半導体装置及びその製造方法 |
KR960009995B1 (ko) * | 1992-07-31 | 1996-07-25 | 삼성전자 주식회사 | 반도체 장치의 제조 방법 및 그 구조 |
US5342801A (en) * | 1993-03-08 | 1994-08-30 | National Semiconductor Corporation | Controllable isotropic plasma etching technique for the suppression of stringers in memory cells |
US5429966A (en) * | 1993-07-22 | 1995-07-04 | National Science Council | Method of fabricating a textured tunnel oxide for EEPROM applications |
US5385856A (en) * | 1993-12-02 | 1995-01-31 | United Microelectronics Corporation | Manufacture of the fieldless split-gate EPROM/Flash EPROM |
JP2924622B2 (ja) * | 1993-12-28 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
US5716864A (en) * | 1994-07-22 | 1998-02-10 | Nkk Corporation | Method of manufacturing a non-volatile semiconductor memory device with peripheral transistor |
TW295695B (de) * | 1994-09-19 | 1997-01-11 | Motorola Inc | |
JP3600326B2 (ja) * | 1994-09-29 | 2004-12-15 | 旺宏電子股▲ふん▼有限公司 | 不揮発性半導体メモリ装置およびその製造方法 |
JPH08213572A (ja) * | 1994-11-30 | 1996-08-20 | Nkk Corp | 不揮発性半導体装置およびその製造方法 |
EP1111673A1 (de) * | 1995-05-10 | 2001-06-27 | STMicroelectronics S.r.l. | Herstellungsverfahren eines integrierten MOS-Schaltkreises mit Bestandteilen mit unterschiedlichen Dielektrika |
US5834351A (en) * | 1995-08-25 | 1998-11-10 | Macronix International, Co. Ltd. | Nitridation process with peripheral region protection |
US5830772A (en) * | 1995-09-08 | 1998-11-03 | United Microelectronicscorp. | Method for fabricating isolating regions for buried conductors |
EP0785570B1 (de) * | 1996-01-22 | 2002-12-04 | STMicroelectronics S.r.l. | Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher |
KR100199382B1 (ko) * | 1996-06-27 | 1999-06-15 | 김영환 | 플래쉬 메모리 소자의 제조방법 |
KR19980033279A (ko) * | 1996-10-29 | 1998-07-25 | 윌리엄비.켐플러 | 개선된 소거 가능한 프로그램 가능 판독 전용 메모리 및 그 제조 방법 |
EP0993036A1 (de) * | 1998-10-09 | 2000-04-12 | STMicroelectronics S.r.l. | Verfahren zur Herstellung einer integrierten Halbleiteranordnung mit einem Feldeffekttransistor mit schwebendem Gate und einem logischen Feldeffekttransistor, und entsprechende Anordnung |
US6110782A (en) * | 1998-11-19 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method to combine high voltage device and salicide process |
JP3314807B2 (ja) | 1998-11-26 | 2002-08-19 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100343151B1 (ko) * | 1999-10-28 | 2002-07-05 | 김덕중 | Sipos를 이용한 고전압 반도체소자 및 그 제조방법 |
US6262455B1 (en) * | 1999-11-02 | 2001-07-17 | Philips Semiconductor, Inc. | Method of forming dual gate oxide layers of varying thickness on a single substrate |
JP3450770B2 (ja) | 1999-11-29 | 2003-09-29 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6685754B2 (en) * | 2001-03-06 | 2004-02-03 | Alchemix Corporation | Method for the production of hydrogen-containing gaseous mixtures |
JP3921363B2 (ja) * | 2001-08-20 | 2007-05-30 | 松下電器産業株式会社 | 不揮発性半導体記憶装置の製造方法 |
US20030232507A1 (en) * | 2002-06-12 | 2003-12-18 | Macronix International Co., Ltd. | Method for fabricating a semiconductor device having an ONO film |
US7867844B2 (en) | 2008-05-28 | 2011-01-11 | Micron Technology, Inc. | Methods of forming NAND cell units |
US10879250B2 (en) * | 2017-08-29 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53124084A (en) * | 1977-04-06 | 1978-10-30 | Hitachi Ltd | Semiconductor memory device containing floating type poly silicon layer and its manufacture |
JPS56120166A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
JPS577162A (en) * | 1980-06-17 | 1982-01-14 | Toshiba Corp | Nonvolatile semiconductor memory and manufacture therefor |
JPS5713772A (en) * | 1980-06-30 | 1982-01-23 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JP2515715B2 (ja) * | 1984-02-24 | 1996-07-10 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
US4663645A (en) * | 1984-05-23 | 1987-05-05 | Hitachi, Ltd. | Semiconductor device of an LDD structure having a floating gate |
JPS6142171A (ja) * | 1984-08-02 | 1986-02-28 | Ricoh Co Ltd | 不揮発性半導体メモリ装置の製造方法 |
KR940002772B1 (ko) * | 1984-08-31 | 1994-04-02 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체 집적회로 장치 및 그 제조방법 |
JPS61136274A (ja) * | 1984-12-07 | 1986-06-24 | Toshiba Corp | 半導体装置 |
US4598460A (en) * | 1984-12-10 | 1986-07-08 | Solid State Scientific, Inc. | Method of making a CMOS EPROM with independently selectable thresholds |
US4635347A (en) * | 1985-03-29 | 1987-01-13 | Advanced Micro Devices, Inc. | Method of fabricating titanium silicide gate electrodes and interconnections |
JPH07114264B2 (ja) * | 1985-08-23 | 1995-12-06 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JPH0793381B2 (ja) * | 1985-10-28 | 1995-10-09 | 株式会社日立製作所 | 半導体集積回路装置 |
US4745083A (en) * | 1986-11-19 | 1988-05-17 | Sprague Electric Company | Method of making a fast IGFET |
US4835740A (en) * | 1986-12-26 | 1989-05-30 | Kabushiki Kaisha Toshiba | Floating gate type semiconductor memory device |
IT1225873B (it) * | 1987-07-31 | 1990-12-07 | Sgs Microelettrica S P A Catan | Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura. |
US4830974A (en) * | 1988-01-11 | 1989-05-16 | Atmel Corporation | EPROM fabrication process |
DE3802858A1 (de) * | 1988-02-01 | 1989-08-03 | Fischer Artur Werke Gmbh | Winkelverbindung fuer streben eines spielbaukastens |
US4851361A (en) * | 1988-02-04 | 1989-07-25 | Atmel Corporation | Fabrication process for EEPROMS with high voltage transistors |
US4859619A (en) * | 1988-07-15 | 1989-08-22 | Atmel Corporation | EPROM fabrication process forming tub regions for high voltage devices |
JPH0282581A (ja) * | 1988-09-19 | 1990-03-23 | Hitachi Ltd | 半導体装置の製造方法およびそれにより得られる半導体装置 |
-
1989
- 1989-04-28 JP JP1110505A patent/JP2509697B2/ja not_active Expired - Fee Related
-
1990
- 1990-04-27 EP EP90108052A patent/EP0395084B1/de not_active Expired - Lifetime
- 1990-04-27 DE DE69015868T patent/DE69015868T2/de not_active Expired - Fee Related
- 1990-04-28 KR KR1019900006028A patent/KR930002295B1/ko not_active IP Right Cessation
-
1991
- 1991-01-29 US US07/647,699 patent/US5158902A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2509697B2 (ja) | 1996-06-26 |
EP0395084B1 (de) | 1995-01-11 |
EP0395084A2 (de) | 1990-10-31 |
EP0395084A3 (de) | 1992-02-12 |
JPH02288363A (ja) | 1990-11-28 |
US5158902A (en) | 1992-10-27 |
KR900017191A (ko) | 1990-11-15 |
DE69015868T2 (de) | 1995-06-22 |
KR930002295B1 (ko) | 1993-03-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |