DE69024773D1 - Halbleiterspeicherschaltungsanordnung - Google Patents

Halbleiterspeicherschaltungsanordnung

Info

Publication number
DE69024773D1
DE69024773D1 DE69024773T DE69024773T DE69024773D1 DE 69024773 D1 DE69024773 D1 DE 69024773D1 DE 69024773 T DE69024773 T DE 69024773T DE 69024773 T DE69024773 T DE 69024773T DE 69024773 D1 DE69024773 D1 DE 69024773D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
circuit arrangement
memory circuit
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69024773T
Other languages
English (en)
Other versions
DE69024773T2 (de
Inventor
Hiroyuki Motegi
Hideaki Uchida
Yasunori Kuwashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69024773D1 publication Critical patent/DE69024773D1/de
Application granted granted Critical
Publication of DE69024773T2 publication Critical patent/DE69024773T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
DE69024773T 1989-11-15 1990-11-13 Halbleiterspeicherschaltungsanordnung Expired - Fee Related DE69024773T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1294986A JPH03156795A (ja) 1989-11-15 1989-11-15 半導体メモリ回路装置

Publications (2)

Publication Number Publication Date
DE69024773D1 true DE69024773D1 (de) 1996-02-22
DE69024773T2 DE69024773T2 (de) 1996-06-27

Family

ID=17814868

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69024773T Expired - Fee Related DE69024773T2 (de) 1989-11-15 1990-11-13 Halbleiterspeicherschaltungsanordnung

Country Status (5)

Country Link
US (1) US5241506A (de)
EP (1) EP0432482B1 (de)
JP (1) JPH03156795A (de)
KR (1) KR940000613B1 (de)
DE (1) DE69024773T2 (de)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384504A (en) * 1992-10-22 1995-01-24 Dickinson; Alexander G. Sense amplifier powered from bit lines and having regeneratively cross-coupling means
JP2870328B2 (ja) * 1992-11-12 1999-03-17 日本電気株式会社 不揮発性半導体記憶装置
KR960011207B1 (ko) * 1993-11-17 1996-08-21 김광호 반도체 메모리 장치의 데이타 센싱방법 및 그 회로
JP3220035B2 (ja) * 1997-02-27 2001-10-22 エヌイーシーマイクロシステム株式会社 スタチック型半導体記憶装置
EP0869506B1 (de) * 1997-04-03 2003-07-02 STMicroelectronics S.r.l. Speicheranordnung mit vermindertem Leistungsverlust
US5999482A (en) * 1997-10-24 1999-12-07 Artisan Components, Inc. High speed memory self-timing circuitry and methods for implementing the same
US6388931B1 (en) * 1999-02-25 2002-05-14 Micron Technology, Inc. Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
US6791555B1 (en) 2000-06-23 2004-09-14 Micron Technology, Inc. Apparatus and method for distributed memory control in a graphics processing system
US20030101312A1 (en) * 2001-11-26 2003-05-29 Doan Trung T. Machine state storage apparatus and method
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7200024B2 (en) 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7254331B2 (en) 2002-08-09 2007-08-07 Micron Technology, Inc. System and method for multiple bit optical data transmission in memory systems
US7149874B2 (en) 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7102907B2 (en) 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
TWI251183B (en) * 2003-05-16 2006-03-11 Toshiba Matsushita Display Tec Active matrix display device
US7245145B2 (en) 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7107415B2 (en) 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7428644B2 (en) 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7389364B2 (en) 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US7210059B2 (en) 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7310752B2 (en) 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7194593B2 (en) 2003-09-18 2007-03-20 Micron Technology, Inc. Memory hub with integrated non-volatile memory
US7120743B2 (en) * 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7188219B2 (en) 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7181584B2 (en) 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
US7412574B2 (en) 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7366864B2 (en) 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7447240B2 (en) 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US6980042B2 (en) 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7590797B2 (en) 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7222213B2 (en) * 2004-05-17 2007-05-22 Micron Technology, Inc. System and method for communicating the synchronization status of memory modules during initialization of the memory modules
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
US7310748B2 (en) 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7392331B2 (en) 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
US7685483B1 (en) * 2005-06-20 2010-03-23 Lattice Semiconductor Corporation Design features for testing integrated circuits
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US10943670B1 (en) * 2019-08-29 2021-03-09 Arm Limited Dummy wordline design techniques
US11200927B2 (en) 2020-04-08 2021-12-14 Micron Technology, Inc. Timing signal delay compensation in a memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2600808A1 (fr) * 1986-06-26 1987-12-31 Dolphin Integration Sa Plan memoire a lecture rapide
JPH0642318B2 (ja) * 1988-01-18 1994-06-01 株式会社東芝 半導体メモリ
JPH0715952B2 (ja) * 1988-04-13 1995-02-22 株式会社東芝 半導体記憶装置
EP0576046B1 (de) * 1988-06-24 1996-03-27 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung

Also Published As

Publication number Publication date
KR940000613B1 (ko) 1994-01-26
JPH03156795A (ja) 1991-07-04
EP0432482B1 (de) 1996-01-10
KR910010519A (ko) 1991-06-29
DE69024773T2 (de) 1996-06-27
EP0432482A2 (de) 1991-06-19
US5241506A (en) 1993-08-31
EP0432482A3 (en) 1992-03-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee