DE69033339T2 - Mechanismus und Verfahren zur Vorhersage von Unterprogrammrücksprüngen - Google Patents

Mechanismus und Verfahren zur Vorhersage von Unterprogrammrücksprüngen

Info

Publication number
DE69033339T2
DE69033339T2 DE69033339T DE69033339T DE69033339T2 DE 69033339 T2 DE69033339 T2 DE 69033339T2 DE 69033339 T DE69033339 T DE 69033339T DE 69033339 T DE69033339 T DE 69033339T DE 69033339 T2 DE69033339 T2 DE 69033339T2
Authority
DE
Germany
Prior art keywords
subroutine returns
predicting
predicting subroutine
returns
subroutine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033339T
Other languages
English (en)
Other versions
DE69033339D1 (de
Inventor
Simon C Steely
David J Sager
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE69033339D1 publication Critical patent/DE69033339D1/de
Application granted granted Critical
Publication of DE69033339T2 publication Critical patent/DE69033339T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address
DE69033339T 1989-12-18 1990-11-27 Mechanismus und Verfahren zur Vorhersage von Unterprogrammrücksprüngen Expired - Fee Related DE69033339T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/451,943 US5179673A (en) 1989-12-18 1989-12-18 Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline

Publications (2)

Publication Number Publication Date
DE69033339D1 DE69033339D1 (de) 1999-12-09
DE69033339T2 true DE69033339T2 (de) 2000-08-03

Family

ID=23794364

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033339T Expired - Fee Related DE69033339T2 (de) 1989-12-18 1990-11-27 Mechanismus und Verfahren zur Vorhersage von Unterprogrammrücksprüngen

Country Status (6)

Country Link
US (1) US5179673A (de)
EP (1) EP0433709B1 (de)
JP (1) JPH06161748A (de)
KR (1) KR940009378B1 (de)
CA (1) CA2032320A1 (de)
DE (1) DE69033339T2 (de)

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US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JP2773471B2 (ja) * 1991-07-24 1998-07-09 日本電気株式会社 情報処理装置
JP3730252B2 (ja) * 1992-03-31 2005-12-21 トランスメタ コーポレイション レジスタ名称変更方法及び名称変更システム
WO1993022722A1 (en) * 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
EP1107111A3 (de) 1992-12-31 2002-02-06 Seiko Epson Corporation System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5604877A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for resolving return from subroutine instructions in a computer processor
US5758142A (en) * 1994-05-31 1998-05-26 Digital Equipment Corporation Trainable apparatus for predicting instruction outcomes in pipelined processors
US5896528A (en) * 1995-03-03 1999-04-20 Fujitsu Limited Superscalar processor with multiple register windows and speculative return address generation
US5968169A (en) * 1995-06-07 1999-10-19 Advanced Micro Devices, Inc. Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses
US5854921A (en) * 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5864707A (en) 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5958039A (en) * 1997-10-28 1999-09-28 Microchip Technology Incorporated Master-slave latches and post increment/decrement operations
US6044456A (en) * 1998-01-05 2000-03-28 Intel Corporation Electronic system and method for maintaining synchronization of multiple front-end pipelines
US20050149694A1 (en) * 1998-12-08 2005-07-07 Mukesh Patel Java hardware accelerator using microcode engine
US6289444B1 (en) 1999-06-02 2001-09-11 International Business Machines Corporation Method and apparatus for subroutine call-return prediction
US6304962B1 (en) 1999-06-02 2001-10-16 International Business Machines Corporation Method and apparatus for prefetching superblocks in a computer processing system
EP1197847A3 (de) * 2000-10-10 2003-05-21 Nazomi Communications Inc. Java-Hardwarebeschleuniger mit Mikrokodemaschine
US20020080388A1 (en) * 2000-12-27 2002-06-27 Sharp Laboratories Of America, Inc. Dynamic method for determining performance of network connected printing devices in a tandem configuration
US20040049666A1 (en) * 2002-09-11 2004-03-11 Annavaram Murali M. Method and apparatus for variable pop hardware return address stack
JP2006040173A (ja) * 2004-07-29 2006-02-09 Fujitsu Ltd 分岐予測装置および分岐予測方法
US7975132B2 (en) * 2009-03-04 2011-07-05 Via Technologies, Inc. Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor
US9317293B2 (en) * 2012-11-28 2016-04-19 Qualcomm Incorporated Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media
US9411590B2 (en) * 2013-03-15 2016-08-09 Qualcomm Incorporated Method to improve speed of executing return branch instructions in a processor
US20240036864A1 (en) * 2022-08-01 2024-02-01 Qualcomm Incorporated Apparatus employing wrap tracking for addressing data overflow

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US3794980A (en) * 1971-04-21 1974-02-26 Cogar Corp Apparatus and method for controlling sequential execution of instructions and nesting of subroutines in a data processor
US4649472A (en) * 1981-02-04 1987-03-10 Burroughs Corporation Multi-phase subroutine control circuitry
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4594659A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Method and apparatus for prefetching instructions for a central execution pipeline unit
US4586127A (en) * 1982-11-03 1986-04-29 Burroughs Corp. Multiple control stores for a pipelined microcontroller
US4611278A (en) * 1983-04-01 1986-09-09 Honeywell Information Systems Inc. Wraparound buffer for repetitive decimal numeric operations
JPS6054049A (ja) * 1983-09-02 1985-03-28 Hitachi Ltd デ−タ処理装置におけるサブル−チンリンク制御方式
US5008807A (en) * 1984-07-05 1991-04-16 Texas Instruments Incorporated Data processing apparatus with abbreviated jump field
JPS62152043A (ja) * 1985-12-26 1987-07-07 Nec Corp 命令コ−ドアクセス制御方式
US4773041A (en) * 1986-06-02 1988-09-20 Unisys Corporation System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor
JPS62285140A (ja) * 1986-06-04 1987-12-11 Hitachi Ltd 情報処理装置
US4814978A (en) * 1986-07-15 1989-03-21 Dataflow Computer Corporation Dataflow processing element, multiprocessor, and processes
JPH06100967B2 (ja) * 1987-06-10 1994-12-12 三菱電機株式会社 パイプライン処理機構を持つデータ処理装置および処理方法
JPH0820952B2 (ja) * 1988-03-01 1996-03-04 三菱電機株式会社 パイプライン処理機構を持つデータ処理装置
US4890221A (en) * 1988-04-01 1989-12-26 Digital Equipment Corporation Apparatus and method for reconstructing a microstack
US5040137A (en) * 1989-12-13 1991-08-13 Audio Animation Random access FIR filtering

Also Published As

Publication number Publication date
DE69033339D1 (de) 1999-12-09
EP0433709A3 (en) 1993-05-12
EP0433709A2 (de) 1991-06-26
KR940009378B1 (en) 1994-10-07
EP0433709B1 (de) 1999-11-03
KR910012914A (ko) 1991-08-08
JPH06161748A (ja) 1994-06-10
CA2032320A1 (en) 1991-06-19
US5179673A (en) 1993-01-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN

8339 Ceased/non-payment of the annual fee