DE69119826T2 - Halbleiter-Kontaktöffnungsstruktur und -verfahren - Google Patents

Halbleiter-Kontaktöffnungsstruktur und -verfahren

Info

Publication number
DE69119826T2
DE69119826T2 DE69119826T DE69119826T DE69119826T2 DE 69119826 T2 DE69119826 T2 DE 69119826T2 DE 69119826 T DE69119826 T DE 69119826T DE 69119826 T DE69119826 T DE 69119826T DE 69119826 T2 DE69119826 T2 DE 69119826T2
Authority
DE
Germany
Prior art keywords
contact opening
opening structure
semiconductor contact
semiconductor
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69119826T
Other languages
English (en)
Other versions
DE69119826D1 (de
Inventor
Fu-Tai Liou
Charles Ralph Spinner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24055528&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69119826(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69119826D1 publication Critical patent/DE69119826D1/de
Publication of DE69119826T2 publication Critical patent/DE69119826T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76858After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/97Specified etch stop material
DE69119826T 1990-04-30 1991-03-25 Halbleiter-Kontaktöffnungsstruktur und -verfahren Expired - Fee Related DE69119826T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/516,425 US5070391A (en) 1989-11-30 1990-04-30 Semiconductor contact via structure and method

Publications (2)

Publication Number Publication Date
DE69119826D1 DE69119826D1 (de) 1996-07-04
DE69119826T2 true DE69119826T2 (de) 1996-10-02

Family

ID=24055528

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119826T Expired - Fee Related DE69119826T2 (de) 1990-04-30 1991-03-25 Halbleiter-Kontaktöffnungsstruktur und -verfahren

Country Status (5)

Country Link
US (2) US5070391A (de)
EP (1) EP0455341B1 (de)
JP (1) JPH04229618A (de)
KR (1) KR100205444B1 (de)
DE (1) DE69119826T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280190A (en) * 1991-03-21 1994-01-18 Industrial Technology Research Institute Self aligned emitter/runner integrated circuit
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5331116A (en) * 1992-04-30 1994-07-19 Sgs-Thomson Microelectronics, Inc. Structure and method for forming contact structures in integrated circuits
US5747360A (en) * 1993-09-17 1998-05-05 Applied Materials, Inc. Method of metalizing a semiconductor wafer
DE69533823D1 (de) * 1994-12-29 2005-01-05 St Microelectronics Inc Elektrische Verbindungsstruktur auf einer integrierten Schaltungsanordnung mit einem Zapfen mit vergrössertem Kopf
EP1098366A1 (de) * 1994-12-29 2001-05-09 STMicroelectronics, Inc. Halbleiterverbindungsstruktur und Verfahren
US6191484B1 (en) 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5844297A (en) * 1995-09-26 1998-12-01 Symbios, Inc. Antifuse device for use on a field programmable interconnect chip
US5963830A (en) * 1996-08-02 1999-10-05 Mosel Vitelic Incorporated Method of forming a TiN/W barrier layer for a hot Al plug
KR100470923B1 (ko) * 1997-05-16 2005-05-10 매그나칩 반도체 유한회사 반도체장치의금속배선형성방법
US6372633B1 (en) 1998-07-08 2002-04-16 Applied Materials, Inc. Method and apparatus for forming metal interconnects
US6969909B2 (en) * 2002-12-20 2005-11-29 Vlt, Inc. Flip chip FET device
US7038917B2 (en) * 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
KR102307633B1 (ko) 2014-12-10 2021-10-06 삼성전자주식회사 반도체 소자 및 그 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3499213A (en) * 1965-09-30 1970-03-10 Texas Instruments Inc Method of making a multilayer contact system for semiconductor devices
JPS5726431A (en) * 1980-07-24 1982-02-12 Mitsubishi Electric Corp Forming method for electrode and wiring layer of semiconductor device
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
JPS62259469A (ja) * 1986-05-06 1987-11-11 Hitachi Ltd 半導体装置
US4824803A (en) * 1987-06-22 1989-04-25 Standard Microsystems Corporation Multilayer metallization method for integrated circuits
JP2630403B2 (ja) * 1987-08-19 1997-07-16 富士通株式会社 半導体装置とその製造方法
US4837609A (en) * 1987-09-09 1989-06-06 American Telephone And Telegraph Company, At&T Bell Laboratories Semiconductor devices having superconducting interconnects
JPH01230253A (ja) * 1988-03-10 1989-09-13 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5110762A (en) * 1988-07-07 1992-05-05 Kabushiki Kaisha Toshiba Manufacturing a wiring formed inside a semiconductor device
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection

Also Published As

Publication number Publication date
EP0455341A3 (en) 1992-06-03
EP0455341A2 (de) 1991-11-06
US5070391A (en) 1991-12-03
EP0455341B1 (de) 1996-05-29
KR100205444B1 (ko) 1999-07-01
DE69119826D1 (de) 1996-07-04
US6455412B1 (en) 2002-09-24
JPH04229618A (ja) 1992-08-19
KR910019178A (ko) 1991-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee