DE69119871D1 - Verfahren zum Ätzen von Schichten mit vorgegebener Tiefe in integrierten Schaltungen - Google Patents

Verfahren zum Ätzen von Schichten mit vorgegebener Tiefe in integrierten Schaltungen

Info

Publication number
DE69119871D1
DE69119871D1 DE69119871T DE69119871T DE69119871D1 DE 69119871 D1 DE69119871 D1 DE 69119871D1 DE 69119871 T DE69119871 T DE 69119871T DE 69119871 T DE69119871 T DE 69119871T DE 69119871 D1 DE69119871 D1 DE 69119871D1
Authority
DE
Germany
Prior art keywords
integrated circuits
predetermined depth
etching layers
etching
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69119871T
Other languages
English (en)
Other versions
DE69119871T2 (de
Inventor
Michel Haond
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zarbana Digital Fund LLC
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Publication of DE69119871D1 publication Critical patent/DE69119871D1/de
Application granted granted Critical
Publication of DE69119871T2 publication Critical patent/DE69119871T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
DE69119871T 1990-11-16 1991-11-14 Verfahren zum Ätzen von Schichten mit vorgegebener Tiefe in integrierten Schaltungen Expired - Lifetime DE69119871T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9014306A FR2669466B1 (fr) 1990-11-16 1990-11-16 Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant.

Publications (2)

Publication Number Publication Date
DE69119871D1 true DE69119871D1 (de) 1996-07-04
DE69119871T2 DE69119871T2 (de) 1996-11-28

Family

ID=9402286

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119871T Expired - Lifetime DE69119871T2 (de) 1990-11-16 1991-11-14 Verfahren zum Ätzen von Schichten mit vorgegebener Tiefe in integrierten Schaltungen

Country Status (5)

Country Link
US (1) US5330617A (de)
EP (1) EP0487380B1 (de)
JP (1) JPH06177090A (de)
DE (1) DE69119871T2 (de)
FR (1) FR2669466B1 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4029912A1 (de) * 1990-09-21 1992-03-26 Philips Patentverwaltung Verfahren zur bildung mindestens eines grabens in einer substratschicht
US5465859A (en) * 1994-04-28 1995-11-14 International Business Machines Corporation Dual phase and hybrid phase shifting mask fabrication using a surface etch monitoring technique
US7550794B2 (en) 2002-09-20 2009-06-23 Idc, Llc Micromechanical systems device comprising a displaceable electrode and a charge-trapping layer
US7297471B1 (en) 2003-04-15 2007-11-20 Idc, Llc Method for manufacturing an array of interferometric modulators
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal
US5776808A (en) * 1996-12-26 1998-07-07 Siemens Aktiengesellschaft Pad stack with a poly SI etch stop for TEOS mask removal with RIE
US6794119B2 (en) 2002-02-12 2004-09-21 Iridigm Display Corporation Method for fabricating a structure for a microelectromechanical systems (MEMS) device
US7781850B2 (en) 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
TW570896B (en) * 2003-05-26 2004-01-11 Prime View Int Co Ltd A method for fabricating an interference display cell
US7221495B2 (en) * 2003-06-24 2007-05-22 Idc Llc Thin film precursor stack for MEMS manufacturing
TWI231865B (en) * 2003-08-26 2005-05-01 Prime View Int Co Ltd An interference display cell and fabrication method thereof
TW593126B (en) * 2003-09-30 2004-06-21 Prime View Int Co Ltd A structure of a micro electro mechanical system and manufacturing the same
US7405861B2 (en) 2004-09-27 2008-07-29 Idc, Llc Method and device for protecting interferometric modulators from electrostatic discharge
US7553684B2 (en) * 2004-09-27 2009-06-30 Idc, Llc Method of fabricating interferometric devices using lift-off processing techniques
US7161730B2 (en) * 2004-09-27 2007-01-09 Idc, Llc System and method for providing thermal compensation for an interferometric modulator display
US7369296B2 (en) 2004-09-27 2008-05-06 Idc, Llc Device and method for modifying actuation voltage thresholds of a deformable membrane in an interferometric modulator
US7417783B2 (en) 2004-09-27 2008-08-26 Idc, Llc Mirror and mirror layer for optical modulator and method
US7420728B2 (en) 2004-09-27 2008-09-02 Idc, Llc Methods of fabricating interferometric modulators by selectively removing a material
US7373026B2 (en) 2004-09-27 2008-05-13 Idc, Llc MEMS device fabricated on a pre-patterned substrate
US7349136B2 (en) 2004-09-27 2008-03-25 Idc, Llc Method and device for a display having transparent components integrated therein
US7684104B2 (en) 2004-09-27 2010-03-23 Idc, Llc MEMS using filler material and method
US20060065622A1 (en) * 2004-09-27 2006-03-30 Floyd Philip D Method and system for xenon fluoride etching with enhanced efficiency
US7492502B2 (en) 2004-09-27 2009-02-17 Idc, Llc Method of fabricating a free-standing microstructure
TW200628877A (en) 2005-02-04 2006-08-16 Prime View Int Co Ltd Method of manufacturing optical interference type color display
JP2009503564A (ja) 2005-07-22 2009-01-29 クアルコム，インコーポレイテッド Ｍｅｍｓデバイスのための支持構造、およびその方法
US7630114B2 (en) 2005-10-28 2009-12-08 Idc, Llc Diffusion barrier layer for MEMS devices
US7795061B2 (en) * 2005-12-29 2010-09-14 Qualcomm Mems Technologies, Inc. Method of creating MEMS device cavities by a non-etching process
US7382515B2 (en) 2006-01-18 2008-06-03 Qualcomm Mems Technologies, Inc. Silicon-rich silicon nitrides as etch stops in MEMS manufacture
US7547568B2 (en) 2006-02-22 2009-06-16 Qualcomm Mems Technologies, Inc. Electrical conditioning of MEMS device and insulating layer thereof
US7450295B2 (en) 2006-03-02 2008-11-11 Qualcomm Mems Technologies, Inc. Methods for producing MEMS with protective coatings using multi-component sacrificial layers
US20070228156A1 (en) * 2006-03-28 2007-10-04 Household Corporation Interoperability facilitator
US7643203B2 (en) * 2006-04-10 2010-01-05 Qualcomm Mems Technologies, Inc. Interferometric optical display system with broadband characteristics
US7417784B2 (en) * 2006-04-19 2008-08-26 Qualcomm Mems Technologies, Inc. Microelectromechanical device and method utilizing a porous surface
US7711239B2 (en) * 2006-04-19 2010-05-04 Qualcomm Mems Technologies, Inc. Microelectromechanical device and method utilizing nanoparticles
US7623287B2 (en) 2006-04-19 2009-11-24 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7527996B2 (en) 2006-04-19 2009-05-05 Qualcomm Mems Technologies, Inc. Non-planar surface structures and process for microelectromechanical systems
US7369292B2 (en) 2006-05-03 2008-05-06 Qualcomm Mems Technologies, Inc. Electrode and interconnect materials for MEMS devices
US7405863B2 (en) 2006-06-01 2008-07-29 Qualcomm Mems Technologies, Inc. Patterning of mechanical layer in MEMS to reduce stresses at supports
US7321457B2 (en) * 2006-06-01 2008-01-22 Qualcomm Incorporated Process and structure for fabrication of MEMS device having isolated edge posts
US7763546B2 (en) 2006-08-02 2010-07-27 Qualcomm Mems Technologies, Inc. Methods for reducing surface charges during the manufacture of microelectromechanical systems devices
US7719752B2 (en) 2007-05-11 2010-05-18 Qualcomm Mems Technologies, Inc. MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same
US7553770B2 (en) 2007-06-06 2009-06-30 Micron Technology, Inc. Reverse masking profile improvements in high aspect ratio etch
US7719754B2 (en) * 2008-09-30 2010-05-18 Qualcomm Mems Technologies, Inc. Multi-thickness layers for MEMS and mask-saving sequence for same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
US4174252A (en) * 1978-07-26 1979-11-13 Rca Corporation Method of defining contact openings in insulating layers on semiconductor devices without the formation of undesirable pinholes
US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
US4436593A (en) * 1981-07-13 1984-03-13 Memorex Corporation Self-aligned pole tips
DE3275447D1 (en) * 1982-07-03 1987-03-19 Ibm Deutschland Process for the formation of grooves having essentially vertical lateral silicium walls by reactive ion etching
US4801554A (en) * 1983-03-31 1989-01-31 Bbc Brown, Boveri & Company, Limited Process for manufacturing a power semiconductor component
EP0166893B1 (de) * 1984-05-04 1989-01-18 BBC Brown Boveri AG Trockenätzverfahren
US4628588A (en) * 1984-06-25 1986-12-16 Texas Instruments Incorporated Molybdenum-metal mask for definition and etch of oxide-encapsulated metal gate
US4576834A (en) * 1985-05-20 1986-03-18 Ncr Corporation Method for forming trench isolation structures
JPS62502646A (ja) * 1985-09-27 1987-10-08 バロ−ス・コ−ポレ−シヨン ポリイミドに先細形状のビア・ホ−ルを作成する方法
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
US4837180A (en) * 1987-07-09 1989-06-06 Industrial Technology Research Institute Ladder gate LDDFET
JPH01117034A (ja) * 1987-10-29 1989-05-09 Fujitsu Ltd トレンチエッチング方法
US4832789A (en) * 1988-04-08 1989-05-23 American Telephone And Telegrph Company, At&T Bell Laboratories Semiconductor devices having multi-level metal interconnects
US5118384A (en) * 1990-04-03 1992-06-02 International Business Machines Corporation Reactive ion etching buffer mask
US5047117A (en) * 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer

Also Published As

Publication number Publication date
JPH06177090A (ja) 1994-06-24
US5330617A (en) 1994-07-19
FR2669466A1 (fr) 1992-05-22
EP0487380B1 (de) 1996-05-29
EP0487380A1 (de) 1992-05-27
FR2669466B1 (fr) 1997-11-07
DE69119871T2 (de) 1996-11-28

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FAHRENHEIT THERMOSCOPE LLC (N.D.GES. D. STAATES DE