DE69121122T2 - Integrierter Schaltkreis - Google Patents

Integrierter Schaltkreis

Info

Publication number
DE69121122T2
DE69121122T2 DE69121122T DE69121122T DE69121122T2 DE 69121122 T2 DE69121122 T2 DE 69121122T2 DE 69121122 T DE69121122 T DE 69121122T DE 69121122 T DE69121122 T DE 69121122T DE 69121122 T2 DE69121122 T2 DE 69121122T2
Authority
DE
Germany
Prior art keywords
logic
programmable
macrocells
array
product term
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69121122T
Other languages
English (en)
Other versions
DE69121122D1 (de
Inventor
Om P Agrawal
George H Landers
Nicholas A Schmitz
Jerry D Moench
Kerry A Llgenstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vantis Corp
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23949554&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69121122(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69121122D1 publication Critical patent/DE69121122D1/de
Application granted granted Critical
Publication of DE69121122T2 publication Critical patent/DE69121122T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
DE69121122T 1990-03-07 1991-01-18 Integrierter Schaltkreis Expired - Fee Related DE69121122T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/490,808 US5015884A (en) 1985-03-29 1990-03-07 Multiple array high performance programmable logic device family

Publications (2)

Publication Number Publication Date
DE69121122D1 DE69121122D1 (de) 1996-09-05
DE69121122T2 true DE69121122T2 (de) 1997-02-13

Family

ID=23949554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69121122T Expired - Fee Related DE69121122T2 (de) 1990-03-07 1991-01-18 Integrierter Schaltkreis

Country Status (5)

Country Link
US (1) US5015884A (de)
EP (1) EP0445909B1 (de)
JP (1) JP3454834B2 (de)
AT (1) ATE141034T1 (de)
DE (1) DE69121122T2 (de)

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US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5457409A (en) * 1992-08-03 1995-10-10 Advanced Micro Devices, Inc. Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices
US5079451A (en) * 1990-12-13 1992-01-07 Atmel Corporation Programmable logic device with global and local product terms
US5978831A (en) * 1991-03-07 1999-11-02 Lucent Technologies Inc. Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates
US5861760A (en) 1991-04-25 1999-01-19 Altera Corporation Programmable logic device macrocell with improved capability
US5204556A (en) * 1991-05-06 1993-04-20 Lattice Semiconductor Corporation Programmable interconnect structure for logic blocks
US5260611A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic array having local and long distance conductors
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US5371422A (en) * 1991-09-03 1994-12-06 Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
US5282271A (en) * 1991-10-30 1994-01-25 I-Cube Design Systems, Inc. I/O buffering system to a programmable switching apparatus
US5369772A (en) * 1992-05-21 1994-11-29 Compaq Computer Corporation Method of maximizing data pin usage utilizing post-buffer feedback
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EP0584910B1 (de) * 1992-08-03 1996-09-04 Advanced Micro Devices, Inc. Programmierbare logische Vorrichtung
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5362999A (en) * 1993-03-18 1994-11-08 Xilinx, Inc. EPLD chip with hybrid architecture optimized for both speed and flexibility
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5444394A (en) * 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
US5689686A (en) * 1994-07-29 1997-11-18 Cypress Semiconductor Corp. Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
US5848066A (en) * 1994-08-01 1998-12-08 Cypress Semiconductor Corp. Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
US5815726A (en) * 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
US5521529A (en) * 1995-06-02 1996-05-28 Advanced Micro Devices, Inc. Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation
US5818254A (en) * 1995-06-02 1998-10-06 Advanced Micro Devices, Inc. Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices
US6531890B1 (en) 1995-06-02 2003-03-11 Lattice Semiconductor Corporation Programmable optimized-distribution logic allocator for a high-density complex PLD
US5781030A (en) * 1995-06-02 1998-07-14 Advanced Micro Devices, Inc. Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD
US6028446A (en) * 1995-06-06 2000-02-22 Advanced Micro Devices, Inc. Flexible synchronous and asynchronous circuits for a very high density programmable logic device
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
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US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US6229812B1 (en) * 1996-10-28 2001-05-08 Paxonet Communications, Inc. Scheduling techniques for data cells in a data switch
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US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US6191611B1 (en) 1997-10-16 2001-02-20 Altera Corporation Driver circuitry for programmable logic devices with hierarchical interconnection resources
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6243664B1 (en) 1998-10-27 2001-06-05 Cypress Semiconductor Corporation Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
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US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
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US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
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US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
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US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
TW504898B (en) * 2001-04-17 2002-10-01 Himax Tech Inc Distributed data signal converting device and method
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US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
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US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
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Also Published As

Publication number Publication date
EP0445909B1 (de) 1996-07-31
EP0445909A1 (de) 1991-09-11
DE69121122D1 (de) 1996-09-05
US5015884A (en) 1991-05-14
JPH04219021A (ja) 1992-08-10
ATE141034T1 (de) 1996-08-15
JP3454834B2 (ja) 2003-10-06

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Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL

8339 Ceased/non-payment of the annual fee