DE69124669T2 - Einrichtung zur Einstellung des Prüfmodus für den Gebrauch in einem Mikrorechner - Google Patents

Einrichtung zur Einstellung des Prüfmodus für den Gebrauch in einem Mikrorechner

Info

Publication number
DE69124669T2
DE69124669T2 DE69124669T DE69124669T DE69124669T2 DE 69124669 T2 DE69124669 T2 DE 69124669T2 DE 69124669 T DE69124669 T DE 69124669T DE 69124669 T DE69124669 T DE 69124669T DE 69124669 T2 DE69124669 T2 DE 69124669T2
Authority
DE
Germany
Prior art keywords
microcomputer
setting
test mode
test
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124669T
Other languages
English (en)
Other versions
DE69124669D1 (de
Inventor
Hatsuhiro Nagaishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69124669D1 publication Critical patent/DE69124669D1/de
Publication of DE69124669T2 publication Critical patent/DE69124669T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
DE69124669T 1990-11-28 1991-11-28 Einrichtung zur Einstellung des Prüfmodus für den Gebrauch in einem Mikrorechner Expired - Fee Related DE69124669T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2327923A JPH04195546A (ja) 1990-11-28 1990-11-28 マイクロコンピュータのテストモード設定回路

Publications (2)

Publication Number Publication Date
DE69124669D1 DE69124669D1 (de) 1997-03-27
DE69124669T2 true DE69124669T2 (de) 1997-09-11

Family

ID=18204515

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124669T Expired - Fee Related DE69124669T2 (de) 1990-11-28 1991-11-28 Einrichtung zur Einstellung des Prüfmodus für den Gebrauch in einem Mikrorechner

Country Status (4)

Country Link
US (1) US5291425A (de)
EP (1) EP0488281B1 (de)
JP (1) JPH04195546A (de)
DE (1) DE69124669T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260950A (en) * 1991-09-17 1993-11-09 Ncr Corporation Boundary-scan input circuit for a reset pin
JPH05233352A (ja) * 1992-02-19 1993-09-10 Nec Corp マイクロプロセッサ
US5457802A (en) * 1993-05-17 1995-10-10 Motorola, Inc. Integrated circuit pin control apparatus and method thereof in a data processing system
US5428770A (en) * 1993-08-31 1995-06-27 Motorola, Inc. Single-chip microcontroller with efficient peripheral testability
JP2743850B2 (ja) * 1994-12-28 1998-04-22 日本電気株式会社 データ処理装置
JPH10133908A (ja) * 1996-10-29 1998-05-22 Mitsubishi Electric Corp マイクロプロセッサ
US5893923A (en) * 1997-05-12 1999-04-13 Lexmark International, Inc. Microcontroller utilizing a circuit to select during reset process an internal or external memory as base memory
US5764655A (en) * 1997-07-02 1998-06-09 International Business Machines Corporation Built in self test with memory
US6108798A (en) * 1997-07-02 2000-08-22 International Business Machines Corporation Self programmed built in self test
US6230290B1 (en) 1997-07-02 2001-05-08 International Business Machines Corporation Method of self programmed built in self test
US6185712B1 (en) 1998-07-02 2001-02-06 International Business Machines Corporation Chip performance optimization with self programmed built in self test
DE10041697A1 (de) * 2000-08-24 2002-03-14 Infineon Technologies Ag Verfahren zum Testen einer programmgesteuerten Einheit durch eine externe Testvorrichtung
TWI312965B (en) * 2003-02-26 2009-08-01 Novatek Microelectronics Corp Micro-system for burn-in system program from a plug-able subsystem to main memory and method thereof
KR20220021908A (ko) 2019-06-25 2022-02-22 고쿠리츠켄큐카이하츠호진 상교기쥬츠 소고켄큐쇼 와이어 그리드형 편광 소자 및 그 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3893084A (en) * 1973-05-01 1975-07-01 Digital Equipment Corp Memory access control system
US4171536A (en) * 1976-05-03 1979-10-16 International Business Machines Corporation Microprocessor system
DE3207633A1 (de) * 1982-02-26 1983-09-15 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur ueberwachung eines mikroprozessors
JPS59216249A (ja) * 1983-05-23 1984-12-06 Toshiba Corp 集積回路装置
US4677586A (en) * 1985-06-04 1987-06-30 Texas Instruments Incorporated Microcomputer device having test mode substituting external RAM for internal RAM
JPS6267800A (ja) * 1985-09-20 1987-03-27 Hitachi Ltd 半導体集積回路装置
KR880014482A (ko) * 1987-05-27 1988-12-24 미다 가쓰시게 반도체 집적회로 장치
US4833629A (en) * 1987-07-14 1989-05-23 The Johns Hopkins University Apparatus for categorizing and accumulating events
JP2621894B2 (ja) * 1987-12-26 1997-06-18 株式会社東芝 マイクロコンピュータ
JP2827229B2 (ja) * 1988-10-14 1998-11-25 日本電気株式会社 半導体集積回路
US5086505A (en) * 1989-06-30 1992-02-04 Motorola, Inc. Selective individual reset apparatus and method
JPH0389182A (ja) * 1989-08-31 1991-04-15 Sharp Corp 集積回路装置
FR2656940A1 (fr) * 1990-01-09 1991-07-12 Sgs Thomson Microelectronics Circuit integre a microprocesseur fonctionnant en mode rom interne et eprom externe.

Also Published As

Publication number Publication date
EP0488281B1 (de) 1997-02-12
JPH04195546A (ja) 1992-07-15
EP0488281A3 (en) 1993-03-31
US5291425A (en) 1994-03-01
EP0488281A2 (de) 1992-06-03
DE69124669D1 (de) 1997-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee