DE69127036D1 - Halbleiter mit verbessertem Prüfmodus - Google Patents

Halbleiter mit verbessertem Prüfmodus

Info

Publication number
DE69127036D1
DE69127036D1 DE69127036T DE69127036T DE69127036D1 DE 69127036 D1 DE69127036 D1 DE 69127036D1 DE 69127036 T DE69127036 T DE 69127036T DE 69127036 T DE69127036 T DE 69127036T DE 69127036 D1 DE69127036 D1 DE 69127036D1
Authority
DE
Germany
Prior art keywords
semiconductors
test mode
improved test
improved
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127036T
Other languages
English (en)
Other versions
DE69127036T2 (de
Inventor
David Charles Mcclure
Thomas Allyn Coker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69127036D1 publication Critical patent/DE69127036D1/de
Application granted granted Critical
Publication of DE69127036T2 publication Critical patent/DE69127036T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
DE69127036T 1990-07-13 1991-05-31 Halbleiter mit verbessertem Prüfmodus Expired - Fee Related DE69127036T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/552,567 US5265100A (en) 1990-07-13 1990-07-13 Semiconductor memory with improved test mode

Publications (2)

Publication Number Publication Date
DE69127036D1 true DE69127036D1 (de) 1997-09-04
DE69127036T2 DE69127036T2 (de) 1998-01-22

Family

ID=24205893

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127036T Expired - Fee Related DE69127036T2 (de) 1990-07-13 1991-05-31 Halbleiter mit verbessertem Prüfmodus

Country Status (5)

Country Link
US (2) US5265100A (de)
EP (1) EP0472266B1 (de)
JP (1) JPH04229500A (de)
KR (1) KR920003322A (de)
DE (1) DE69127036T2 (de)

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JP3645578B2 (ja) * 1992-09-17 2005-05-11 テキサス インスツルメンツ インコーポレイテツド スマート・メモリの組込み自己検査のための装置と方法
JP2768175B2 (ja) * 1992-10-26 1998-06-25 日本電気株式会社 半導体メモリ
JP2845713B2 (ja) * 1993-03-12 1999-01-13 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
JPH06295599A (ja) * 1993-04-09 1994-10-21 Nec Corp 半導体記憶装置
US5864565A (en) 1993-06-15 1999-01-26 Micron Technology, Inc. Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
US6101618A (en) * 1993-12-22 2000-08-08 Stmicroelectronics, Inc. Method and device for acquiring redundancy information from a packaged memory chip
US5491444A (en) * 1993-12-28 1996-02-13 Sgs-Thomson Microelectronics, Inc. Fuse circuit with feedback disconnect
US5526311A (en) * 1993-12-30 1996-06-11 Intel Corporation Method and circuitry for enabling and permanently disabling test mode access in a flash memory device
US5579326A (en) * 1994-01-31 1996-11-26 Sgs-Thomson Microelectronics, Inc. Method and apparatus for programming signal timing
US5493537A (en) * 1994-02-28 1996-02-20 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with edge transition detection pulse disable
JPH08161899A (ja) * 1994-04-29 1996-06-21 Texas Instr Inc <Ti> メモリデバイスおよび半導体デバイステスト方法
KR0147632B1 (ko) * 1995-04-24 1998-11-02 김광호 반도체 메모리장치의 멀티 비트 테스트방법 및 테스트 회로
US5619460A (en) * 1995-06-07 1997-04-08 International Business Machines Corporation Method of testing a random access memory
US5574692A (en) * 1995-06-07 1996-11-12 Lsi Logic Corporation Memory testing apparatus for microelectronic integrated circuit
US5615164A (en) * 1995-06-07 1997-03-25 International Business Machines Corporation Latched row decoder for a random access memory
US5539753A (en) * 1995-08-10 1996-07-23 International Business Machines Corporation Method and apparatus for output deselecting of data during test
KR100197554B1 (ko) * 1995-09-30 1999-06-15 윤종용 반도체 메모리장치의 고속테스트 방법
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5691950A (en) * 1996-01-19 1997-11-25 Sgs-Thomson Microelectronics, Inc. Device and method for isolating bit lines from a data line
US5802004A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Clocked sense amplifier with wordline tracking
US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
US5619466A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Low-power read circuit and method for controlling a sense amplifier
US5745432A (en) * 1996-01-19 1998-04-28 Sgs-Thomson Microelectronics, Inc. Write driver having a test function
US5848018A (en) * 1996-01-19 1998-12-08 Stmicroelectronics, Inc. Memory-row selector having a test function
EP0801401B1 (de) * 1996-04-02 2003-08-27 STMicroelectronics, Inc. Prüfung und Reparatur einer eingebetteten Speicherschaltung
KR0183856B1 (ko) * 1996-05-17 1999-04-15 김광호 반도체 메모리 장치의 번인 스트레스 회로
US5787097A (en) * 1996-07-22 1998-07-28 Micron Technology, Inc. Output data compression scheme for use in testing IC memories
JP2968733B2 (ja) * 1996-09-13 1999-11-02 日本電気アイシーマイコンシステム株式会社 シリアルバスコントローラ
US5996097A (en) * 1997-04-28 1999-11-30 International Business Machines Corporation Testing logic associated with numerous memory cells in the word or bit dimension in parallel
US5883844A (en) * 1997-05-23 1999-03-16 Stmicroelectronics, Inc. Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof
US6009026A (en) * 1997-07-28 1999-12-28 International Business Machines Corporation Compressed input/output test mode
US6199140B1 (en) * 1997-10-30 2001-03-06 Netlogic Microsystems, Inc. Multiport content addressable memory device and timing signals
US6148364A (en) * 1997-12-30 2000-11-14 Netlogic Microsystems, Inc. Method and apparatus for cascading content addressable memory devices
US6111800A (en) * 1997-12-05 2000-08-29 Cypress Semiconductor Corporation Parallel test for asynchronous memory
JPH11184834A (ja) * 1997-12-25 1999-07-09 Sanyo Electric Co Ltd マイクロコンピュータ
JP4044663B2 (ja) * 1998-02-25 2008-02-06 富士通株式会社 半導体装置
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system
US6381673B1 (en) 1998-07-06 2002-04-30 Netlogic Microsystems, Inc. Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device
KR100365562B1 (ko) * 1998-12-30 2003-02-20 주식회사 하이닉스반도체 반도체 기억소자의 테스트회로
US6574702B2 (en) 1999-02-23 2003-06-03 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a content addressable memory device
US6460112B1 (en) 1999-02-23 2002-10-01 Netlogic Microsystems, Llc Method and apparatus for determining a longest prefix match in a content addressable memory device
US6539455B1 (en) 1999-02-23 2003-03-25 Netlogic Microsystems, Inc. Method and apparatus for determining an exact match in a ternary content addressable memory device
US6892272B1 (en) 1999-02-23 2005-05-10 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a content addressable memory device
US6499081B1 (en) 1999-02-23 2002-12-24 Netlogic Microsystems, Inc. Method and apparatus for determining a longest prefix match in a segmented content addressable memory device
US6137707A (en) * 1999-03-26 2000-10-24 Netlogic Microsystems Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device
KR100339502B1 (ko) * 1999-06-02 2002-05-31 윤종용 다수개의 데이터 라인을 구분되게 테스트하는 통합 데이터 라인 테스트 회로 및 이를 이용하는 테스트 방법
KR100295691B1 (ko) * 1999-06-04 2001-07-12 김영환 디램의 오픈 테스트용 테스트모드회로
US7143231B1 (en) 1999-09-23 2006-11-28 Netlogic Microsystems, Inc. Method and apparatus for performing packet classification for policy-based packet routing
US6944709B2 (en) 1999-09-23 2005-09-13 Netlogic Microsystems, Inc. Content addressable memory with block-programmable mask write mode, word width and priority
US6934795B2 (en) 1999-09-23 2005-08-23 Netlogic Microsystems, Inc. Content addressable memory with programmable word width and programmable priority
US6567340B1 (en) 1999-09-23 2003-05-20 Netlogic Microsystems, Inc. Memory storage cell based array of counters
US7110407B1 (en) 1999-09-23 2006-09-19 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system using enable signals
US7487200B1 (en) 1999-09-23 2009-02-03 Netlogic Microsystems, Inc. Method and apparatus for performing priority encoding in a segmented classification system
US7272027B2 (en) 1999-09-23 2007-09-18 Netlogic Microsystems, Inc. Priority circuit for content addressable memory
US6622201B1 (en) * 2000-01-28 2003-09-16 Advanced Micro Devices, Inc. Chained array of sequential access memories enabling continuous read
KR100346447B1 (ko) * 2000-06-30 2002-07-27 주식회사 하이닉스반도체 반도체 메모리 소자의 병렬 테스트 장치
US7036059B1 (en) * 2001-02-14 2006-04-25 Xilinx, Inc. Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
US6904551B1 (en) * 2001-02-20 2005-06-07 Cypress Semiconductor Corporation Method and circuit for setup and hold detect pass-fail test mode
JP2002260398A (ja) * 2001-03-05 2002-09-13 Mitsubishi Electric Corp マルチビットテスト回路
KR100583152B1 (ko) * 2004-02-19 2006-05-23 주식회사 하이닉스반도체 데이터 억세스타임 측정모드를 갖는 반도체 메모리 소자
US7548473B2 (en) * 2006-04-14 2009-06-16 Purdue Research Foundation Apparatus and methods for determining memory device faults
WO2008044391A1 (fr) * 2006-10-05 2008-04-17 Advantest Corporation Dispositif de contrôle, procédé de contrôle et procédé de fabrication
KR20080033671A (ko) * 2006-10-13 2008-04-17 삼성전자주식회사 테스트 사이클을 감소시키는 반도체 메모리 장치 및 테스트방법
JP2009239259A (ja) * 2008-03-04 2009-10-15 Elpida Memory Inc 半導体装置
US7786724B1 (en) * 2009-04-22 2010-08-31 Advanced Inquiry Systems, Inc. Methods and apparatus for collecting process characterization data after first failure in a group of tested devices
KR20140010663A (ko) * 2012-07-16 2014-01-27 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 테스트 방법

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Also Published As

Publication number Publication date
US5311473A (en) 1994-05-10
EP0472266A3 (en) 1993-03-10
EP0472266A2 (de) 1992-02-26
KR920003322A (ko) 1992-02-29
US5265100A (en) 1993-11-23
EP0472266B1 (de) 1997-07-30
JPH04229500A (ja) 1992-08-18
DE69127036T2 (de) 1998-01-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee