DE69128107T2 - Busanordnung für Speicherzugriff - Google Patents

Busanordnung für Speicherzugriff

Info

Publication number
DE69128107T2
DE69128107T2 DE69128107T DE69128107T DE69128107T2 DE 69128107 T2 DE69128107 T2 DE 69128107T2 DE 69128107 T DE69128107 T DE 69128107T DE 69128107 T DE69128107 T DE 69128107T DE 69128107 T2 DE69128107 T2 DE 69128107T2
Authority
DE
Germany
Prior art keywords
memory access
bus arrangement
bus
arrangement
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128107T
Other languages
English (en)
Other versions
DE69128107D1 (de
Inventor
Subhasis Laha
Dennis Joseph Thompson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69128107D1 publication Critical patent/DE69128107D1/de
Publication of DE69128107T2 publication Critical patent/DE69128107T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE69128107T 1990-05-25 1991-05-15 Busanordnung für Speicherzugriff Expired - Fee Related DE69128107T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US52905190A 1990-05-25 1990-05-25

Publications (2)

Publication Number Publication Date
DE69128107D1 DE69128107D1 (de) 1997-12-11
DE69128107T2 true DE69128107T2 (de) 1998-02-26

Family

ID=24108302

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128107T Expired - Fee Related DE69128107T2 (de) 1990-05-25 1991-05-15 Busanordnung für Speicherzugriff

Country Status (5)

Country Link
US (1) US5490253A (de)
EP (1) EP0458516B1 (de)
JP (1) JP2501375B2 (de)
DE (1) DE69128107T2 (de)
ES (1) ES2109256T3 (de)

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US7050453B1 (en) * 2000-02-17 2006-05-23 Apple Computer, Inc. Method and apparatus for ensuring compatibility on a high performance serial bus
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US6823441B1 (en) 2001-04-20 2004-11-23 Daimlerchrysler Corporation Method of multiplexed address and data bus
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US9588914B2 (en) 2014-04-09 2017-03-07 International Business Machines Corporation Broadcast and unicast communication between non-coherent processors using coherent address operations
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Also Published As

Publication number Publication date
JPH04271452A (ja) 1992-09-28
EP0458516A3 (en) 1992-04-08
JP2501375B2 (ja) 1996-05-29
ES2109256T3 (es) 1998-01-16
US5490253A (en) 1996-02-06
EP0458516A2 (de) 1991-11-27
EP0458516B1 (de) 1997-11-05
DE69128107D1 (de) 1997-12-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee