DE69132757D1 - Vorrichtung zu Parallelserien und zur Serienparallelwandlung von Daten und dadurch entstandenes serielles digitales Nachrichtenübertragungssystem - Google Patents

Vorrichtung zu Parallelserien und zur Serienparallelwandlung von Daten und dadurch entstandenes serielles digitales Nachrichtenübertragungssystem

Info

Publication number
DE69132757D1
DE69132757D1 DE69132757T DE69132757T DE69132757D1 DE 69132757 D1 DE69132757 D1 DE 69132757D1 DE 69132757 T DE69132757 T DE 69132757T DE 69132757 T DE69132757 T DE 69132757T DE 69132757 D1 DE69132757 D1 DE 69132757D1
Authority
DE
Germany
Prior art keywords
parallel
data
transmission system
message transmission
serial digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132757T
Other languages
English (en)
Other versions
DE69132757T2 (de
Inventor
Roland Marbot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sa Les Clayes Sous Bois Fr
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE69132757D1 publication Critical patent/DE69132757D1/de
Publication of DE69132757T2 publication Critical patent/DE69132757T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
DE69132757T 1990-07-11 1991-07-10 Vorrichtung zu Parallelserien und zur Serienparallelwandlung von Daten und dadurch entstandenes serielles digitales Nachrichtenübertragungssystem Expired - Fee Related DE69132757T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9008812A FR2664765B1 (fr) 1990-07-11 1990-07-11 Dispositif de serialisation et de deserialisation de donnees et systeme de transmission numerique de donnees en serie en resultant.

Publications (2)

Publication Number Publication Date
DE69132757D1 true DE69132757D1 (de) 2001-11-15
DE69132757T2 DE69132757T2 (de) 2002-08-08

Family

ID=9398589

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132757T Expired - Fee Related DE69132757T2 (de) 1990-07-11 1991-07-10 Vorrichtung zu Parallelserien und zur Serienparallelwandlung von Daten und dadurch entstandenes serielles digitales Nachrichtenübertragungssystem

Country Status (6)

Country Link
US (1) US5414830A (de)
EP (1) EP0466592B1 (de)
JP (1) JP3130344B2 (de)
CA (1) CA2046241C (de)
DE (1) DE69132757T2 (de)
FR (1) FR2664765B1 (de)

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FR2723494B1 (fr) 1994-08-04 1996-09-06 Bull Sa Procede d'echantillonnage d'un signal numerique en serie
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
GB2309872A (en) * 1996-02-05 1997-08-06 Ibm Digital display apparatus
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6167077A (en) * 1997-12-23 2000-12-26 Lsi Logic Corporation Using multiple high speed serial lines to transmit high data rates while compensating for overall skew
US6192082B1 (en) * 1998-11-13 2001-02-20 Compaq Computer Corporation Digital television data format conversion with automatic parity detection
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6288656B1 (en) * 1999-12-21 2001-09-11 Lsi Logic Corporation Receive deserializer for regenerating parallel data serially transmitted over multiple channels
AU2001257348A1 (en) * 2000-04-28 2001-11-12 Broadcom Corporation Methods and systems for adaptive receiver equalization
DE10066029B4 (de) * 2000-08-23 2005-11-10 Infineon Technologies Ag Analog/Digital-Wandler
US7319720B2 (en) * 2002-01-28 2008-01-15 Microsoft Corporation Stereoscopic video
US20030156649A1 (en) * 2002-01-28 2003-08-21 Abrams Thomas Algie Video and/or audio processing
US6880026B2 (en) * 2002-05-16 2005-04-12 International Business Machines Corporation Method and apparatus for implementing chip-to-chip interconnect bus initialization
US6996650B2 (en) * 2002-05-16 2006-02-07 International Business Machines Corporation Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus
US6707399B1 (en) * 2002-10-10 2004-03-16 Altera Corporation Data realignment techniques for serial-to-parallel conversion
US7606253B2 (en) * 2004-01-12 2009-10-20 Hewlett-Packard Development Company, L.P. Successful transactions
US7454514B2 (en) * 2004-01-12 2008-11-18 Hewlett-Packard Development Company, L.P. Processing data with uncertain arrival time
US7613958B2 (en) 2004-01-12 2009-11-03 Hewlett-Packard Development Company, L.P. Error detection in a system having coupled channels
US7672222B2 (en) * 2004-01-12 2010-03-02 Hewlett-Packard Development Company, L.P. Link failures
US7729427B2 (en) * 2004-02-24 2010-06-01 Intersil Americas Inc. Pseudo-synchronous one wire bidirectional bus interface
US7624213B2 (en) 2005-02-11 2009-11-24 Hewlett-Packard Development Company, L.P. Passing identification information
US7721159B2 (en) * 2005-02-11 2010-05-18 Hewlett-Packard Development Company, L.P. Passing debug information
WO2006013641A1 (ja) * 2004-08-04 2006-02-09 Hitachi, Ltd. 集積回路装置及び信号伝送システム
US7243173B2 (en) * 2004-12-14 2007-07-10 Rockwell Automation Technologies, Inc. Low protocol, high speed serial transfer for intra-board or inter-board data communication
US7392334B2 (en) * 2006-01-17 2008-06-24 Seiko Epson Corporation Circuits and methods for high speed and low power data serialization
WO2020124566A1 (zh) * 2018-12-21 2020-06-25 华为技术有限公司 一种跨时钟域处理电路
US11695400B1 (en) * 2022-08-12 2023-07-04 Qualcomm Incorporated Low-power inter-die communication using delay lines

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US4496934A (en) * 1980-09-05 1985-01-29 Mitsubishi Denki Kabushiki Kaisha Encoding and decoding systems for binary data
US4449119A (en) * 1981-12-14 1984-05-15 International Business Machines Corporation Self-clocking serial decoder
US4628298A (en) * 1984-06-22 1986-12-09 Bei Motion Systems Company, Inc. Chain code encoder
CA1241384A (en) * 1985-10-18 1988-08-30 Stephen C. Carlton Serial-to-parallel converter for high-speed bit streams
JPH0787447B2 (ja) * 1985-12-18 1995-09-20 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド 同期の直列伝送媒体を利用するシステム
JPH0744448B2 (ja) * 1986-03-31 1995-05-15 株式会社東芝 デジタル位相同期ル−プ回路
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
JPH01501752A (ja) * 1987-01-05 1989-06-15 グラマン　エアロスペース　コーポレーション 高速データクロック同期プロセッサ
US5148385A (en) * 1987-02-04 1992-09-15 Texas Instruments Incorporated Serial systolic processor
US4864303A (en) * 1987-02-13 1989-09-05 Board Of Trustees Of The University Of Illinois Encoder/decoder system and methodology utilizing conservative coding with block delimiters, for serial communication
JPS63292185A (ja) * 1987-05-25 1988-11-29 日本電気株式会社 デジタル入出力回路
US4873491A (en) * 1987-10-19 1989-10-10 Wilkins Jeffrey K Phase shift circuit utilizing a variable time delay line
US4901076A (en) * 1987-10-29 1990-02-13 International Business Machines Corporation Circuit for converting between serial and parallel data streams by high speed addressing
JP2531742B2 (ja) * 1988-05-17 1996-09-04 株式会社東芝 電圧制御発振回路
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JPH0773219B2 (ja) * 1988-06-16 1995-08-02 富士通株式会社 並直列変換装置
KR0160279B1 (ko) * 1988-12-20 1998-12-01 이우에 사또시 무선 통신 장치
US4972161A (en) * 1989-06-28 1990-11-20 Digital Equipment Corporation Clock recovery for serial data communications system
US5084891A (en) * 1989-09-08 1992-01-28 Bell Communications Research, Inc. Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system
US5079519A (en) * 1991-02-14 1992-01-07 Notorola, Inc. Digital phase lock loop for a gate array

Also Published As

Publication number Publication date
DE69132757T2 (de) 2002-08-08
FR2664765A1 (fr) 1992-01-17
EP0466592A1 (de) 1992-01-15
JPH04270515A (ja) 1992-09-25
FR2664765B1 (fr) 2003-05-16
JP3130344B2 (ja) 2001-01-31
US5414830A (en) 1995-05-09
CA2046241A1 (fr) 1992-01-12
CA2046241C (fr) 1995-09-26
EP0466592B1 (de) 2001-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR

8339 Ceased/non-payment of the annual fee