DE69208601T2 - Verfahren zur Verbindung von Leiterplatten - Google Patents

Verfahren zur Verbindung von Leiterplatten

Info

Publication number
DE69208601T2
DE69208601T2 DE69208601T DE69208601T DE69208601T2 DE 69208601 T2 DE69208601 T2 DE 69208601T2 DE 69208601 T DE69208601 T DE 69208601T DE 69208601 T DE69208601 T DE 69208601T DE 69208601 T2 DE69208601 T2 DE 69208601T2
Authority
DE
Germany
Prior art keywords
printed circuit
circuit boards
connecting printed
boards
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69208601T
Other languages
English (en)
Other versions
DE69208601D1 (de
Inventor
Koji Matsui
Mitsuru Kimura
Kazuaki Utsumi
Eiichi Ogawa
Hiroshi Komano
Toshimi Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Ohka Kogyo Co Ltd
NEC Corp
Original Assignee
Tokyo Ohka Kogyo Co Ltd
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP35539891A external-priority patent/JP2660943B2/ja
Priority claimed from JP4196255A external-priority patent/JP3050345B2/ja
Application filed by Tokyo Ohka Kogyo Co Ltd, NEC Corp filed Critical Tokyo Ohka Kogyo Co Ltd
Application granted granted Critical
Publication of DE69208601D1 publication Critical patent/DE69208601D1/de
Publication of DE69208601T2 publication Critical patent/DE69208601T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Combinations Of Printed Boards (AREA)
DE69208601T 1991-11-27 1992-11-26 Verfahren zur Verbindung von Leiterplatten Expired - Lifetime DE69208601T2 (de)

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JP35539891A JP2660943B2 (ja) 1991-11-27 1991-11-27 回路基板の接着方法
JP4196255A JP3050345B2 (ja) 1992-06-29 1992-06-29 集積回路素子の接続方法

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Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
EP0645805B1 (de) * 1993-09-29 2000-11-29 Matsushita Electric Industrial Co., Ltd. Verfahren zum Montieren einer Halbleiteranordnung auf einer Schaltungsplatte und eine Schaltungsplatte mit einer Halbleiteranordnung darauf
JP3400164B2 (ja) * 1995-01-23 2003-04-28 三井金属鉱業株式会社 多層プリント配線板およびその製造方法
US5627405A (en) * 1995-07-17 1997-05-06 National Semiconductor Corporation Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer
JP3285294B2 (ja) * 1995-08-08 2002-05-27 太陽誘電株式会社 回路モジュールの製造方法
JPH09148731A (ja) * 1995-11-17 1997-06-06 Fujitsu Ltd 配線基板間の接続構造の製造方法
US6147870A (en) * 1996-01-05 2000-11-14 Honeywell International Inc. Printed circuit assembly having locally enhanced wiring density
US5839188A (en) * 1996-01-05 1998-11-24 Alliedsignal Inc. Method of manufacturing a printed circuit assembly
JP3842362B2 (ja) * 1996-02-28 2006-11-08 株式会社東芝 熱圧着方法および熱圧着装置
US6000126A (en) * 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
JPH11163501A (ja) * 1997-12-02 1999-06-18 Rohm Co Ltd 電子部品の実装方法、およびその方法によって製造された電子回路装置
SE511330C2 (sv) * 1997-12-29 1999-09-13 Ericsson Telefon Ab L M Förfarande för framställning av ett kretskort jämte skärmningselement för skärmning av komponenter på ett dylikt kretskort
US6765652B1 (en) 1998-01-12 2004-07-20 Micron Technology, Inc. Forming thermally curable materials on a support structure in an electronic device
JP3381601B2 (ja) * 1998-01-26 2003-03-04 松下電器産業株式会社 バンプ付電子部品の実装方法
JP3625646B2 (ja) 1998-03-23 2005-03-02 東レエンジニアリング株式会社 フリップチップ実装方法
JP4448617B2 (ja) * 1998-07-01 2010-04-14 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6189208B1 (en) 1998-09-11 2001-02-20 Polymer Flip Chip Corp. Flip chip mounting technique
US6063646A (en) * 1998-10-06 2000-05-16 Japan Rec Co., Ltd. Method for production of semiconductor package
JP3356079B2 (ja) * 1998-10-12 2002-12-09 ソニーケミカル株式会社 遮光性異方性導電性接着フィルム及び液晶表示素子
US6139661A (en) * 1998-10-20 2000-10-31 International Business Machines Corporation Two step SMT method using masked cure
US6410415B1 (en) 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6996151B1 (en) * 1999-11-08 2006-02-07 Lucent Technologies Inc. Tin oxide adhesion layer for metal-dielectric mirrors
KR100463558B1 (ko) * 2000-04-25 2004-12-29 히다치 가세고교 가부시끼가이샤 회로접속용 접착제 및 그것을 사용한 회로접속방법 및 회로접속구조체
JP2001345549A (ja) * 2000-06-01 2001-12-14 Fujitsu Ltd 実装用基板の製造方法及び部品実装方法並びに実装用基板製造装置
US6646364B1 (en) * 2000-07-11 2003-11-11 Honeywell International Inc. MEMS actuator with lower power consumption and lower cost simplified fabrication
US6490786B2 (en) * 2001-04-17 2002-12-10 Visteon Global Technologies, Inc. Circuit assembly and a method for making the same
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) * 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
BR0204183A (pt) * 2002-09-23 2004-06-01 Ian Royce William Pet Conzalez Processo e dispositivo para a aplicação de camadas adesivas curáveis por radiação
JP4351012B2 (ja) 2003-09-25 2009-10-28 浜松ホトニクス株式会社 半導体装置
JP4494745B2 (ja) 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
JP4494746B2 (ja) 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
US7397968B2 (en) * 2003-10-29 2008-07-08 Hewlett-Packard Development Company, L.P. System and method for tone composition
JP4131864B2 (ja) * 2003-11-25 2008-08-13 東京応化工業株式会社 化学増幅型ポジ型感光性熱硬化性樹脂組成物、硬化物の形成方法、及び機能素子の製造方法
US7307005B2 (en) * 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US20060003548A1 (en) * 2004-06-30 2006-01-05 Kobrinsky Mauro J Highly compliant plate for wafer bonding
US7087538B2 (en) * 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
CN100447971C (zh) * 2004-09-15 2008-12-31 精工爱普生株式会社 半导体装置的安装方法、半导体装置及其安装结构
JP4179312B2 (ja) * 2004-09-15 2008-11-12 セイコーエプソン株式会社 半導体装置の実装方法、半導体装置
US20080099331A1 (en) * 2006-01-12 2008-05-01 Chung Yuan Christian University Solid-state urea biosensor and its data acquisition system
JP2008071812A (ja) * 2006-09-12 2008-03-27 Fujikura Ltd 基板間接続構造
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US8018075B2 (en) * 2008-07-11 2011-09-13 Advanced Semiconductor Engineering, Inc. Semiconductor package, method for enhancing the bond of a bonding wire, and method for manufacturing a semiconductor package
TWI436465B (zh) * 2008-07-11 2014-05-01 Advanced Semiconductor Eng 銲線接合結構、銲線接合方法及半導體封裝構造的製造方法
CN101872754B (zh) * 2009-04-21 2012-05-16 日月光半导体制造股份有限公司 焊线接合结构、强化焊线接合的方法及半导体封装构造的制造方法
US8785524B2 (en) * 2010-06-24 2014-07-22 Funai Electric Co., Ltd. Spray coatable adhesive for bonding silicon dies to rigid substrates
US8643165B2 (en) * 2011-02-23 2014-02-04 Texas Instruments Incorporated Semiconductor device having agglomerate terminals
DE102011017708A1 (de) * 2011-04-28 2012-10-31 Elantas Gmbh Harz-Zusammensetzung enthaltend Sorbinsäureester
US9905811B2 (en) * 2012-08-07 2018-02-27 Joled Inc. Production method for joined body
US9331032B2 (en) * 2013-03-06 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding and apparatus for performing the same
US9789675B1 (en) * 2013-07-24 2017-10-17 Google Inc. Method, apparatus and system for providing a uniform laminate structure
CN103607839A (zh) * 2013-10-26 2014-02-26 溧阳市东大技术转移中心有限公司 一种复合挠性基板
CN105448750A (zh) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3706915A (en) * 1970-03-09 1972-12-19 Gen Electric Semiconductor device with low impedance bond
US4157407A (en) * 1978-02-13 1979-06-05 E. I. Du Pont De Nemours And Company Toning and solvent washout process for making conductive interconnections
JPS59204036A (ja) * 1983-05-06 1984-11-19 Dainippon Ink & Chem Inc レジストパタ−ンの形成法
JPS6099566U (ja) * 1983-12-10 1985-07-06 アルプス電気株式会社 プリント基板端子部の接続構造
KR910000998B1 (ko) * 1986-09-12 1991-02-19 마쯔시다덴기산교 가부시기가이샤 전자부품의 실장방법
US4759490A (en) * 1986-10-23 1988-07-26 Fujitsu Limited Method for soldering electronic components onto a printed wiring board using a solder paste
US4749120A (en) * 1986-12-18 1988-06-07 Matsushita Electric Industrial Co., Ltd. Method of connecting a semiconductor device to a wiring board
US4948706A (en) * 1987-12-30 1990-08-14 Hoya Corporation Process for producing transparent substrate having thereon transparent conductive pattern elements separated by light-shielding insulating film, and process for producing surface-colored material
DE3806738C1 (de) * 1988-03-02 1989-09-07 Espe Stiftung & Co Produktions- Und Vertriebs Kg, 8031 Seefeld, De
EP0389756B1 (de) * 1989-02-02 1994-06-01 Matsushita Electric Industrial Co., Ltd. Verfahren zum Zusammensetzen von Halbleiteranordnungen
US4935627A (en) * 1989-03-13 1990-06-19 Honeywell Inc. Electrical interconnection apparatus for achieving precise alignment of hybrid components
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
JPH0738502B2 (ja) * 1989-10-17 1995-04-26 シャープ株式会社 回路基板の接続方法
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
JP2940269B2 (ja) * 1990-12-26 1999-08-25 日本電気株式会社 集積回路素子の接続方法

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SG44626A1 (en) 1997-12-19
EP0544294A2 (de) 1993-06-02
US5318651A (en) 1994-06-07
EP0544294A3 (en) 1993-12-08
EP0544294B1 (de) 1996-02-28
US5545281A (en) 1996-08-13
DE69208601D1 (de) 1996-04-04

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