DE69221611D1 - Vorrichtung und verfahren zum multiplexen von pins zur in-system programmierung - Google Patents

Vorrichtung und verfahren zum multiplexen von pins zur in-system programmierung

Info

Publication number
DE69221611D1
DE69221611D1 DE69221611T DE69221611T DE69221611D1 DE 69221611 D1 DE69221611 D1 DE 69221611D1 DE 69221611 T DE69221611 T DE 69221611T DE 69221611 T DE69221611 T DE 69221611T DE 69221611 D1 DE69221611 D1 DE 69221611D1
Authority
DE
Germany
Prior art keywords
system programming
multiplexing pins
multiplexing
pins
programming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221611T
Other languages
English (en)
Other versions
DE69221611T2 (de
Inventor
Gregg Josephson
Ju Shen
Roy Darling
Chan-Chi Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Application granted granted Critical
Publication of DE69221611D1 publication Critical patent/DE69221611D1/de
Publication of DE69221611T2 publication Critical patent/DE69221611T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1737Controllable logic circuits using multiplexers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
DE69221611T 1991-05-03 1992-04-29 Vorrichtung und verfahren zum multiplexen von pins zur in-system programmierung Expired - Fee Related DE69221611T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/695,356 US5237218A (en) 1991-05-03 1991-05-03 Structure and method for multiplexing pins for in-system programming
PCT/US1992/003597 WO1992020157A1 (en) 1991-05-03 1992-04-29 Structure and method for multiplexing pins for in-system programming

Publications (2)

Publication Number Publication Date
DE69221611D1 true DE69221611D1 (de) 1997-09-18
DE69221611T2 DE69221611T2 (de) 1998-02-12

Family

ID=24792665

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69221611T Expired - Fee Related DE69221611T2 (de) 1991-05-03 1992-04-29 Vorrichtung und verfahren zum multiplexen von pins zur in-system programmierung
DE0582660T Pending DE582660T1 (de) 1991-05-03 1992-04-29 Struktur und verfahren zum multiplexer von anschlüssen bei der programmierung innerhalb eines systems.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE0582660T Pending DE582660T1 (de) 1991-05-03 1992-04-29 Struktur und verfahren zum multiplexer von anschlüssen bei der programmierung innerhalb eines systems.

Country Status (5)

Country Link
US (2) US5237218A (de)
EP (1) EP0582660B1 (de)
JP (1) JP3507488B2 (de)
DE (2) DE69221611T2 (de)
WO (1) WO1992020157A1 (de)

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US5864486A (en) * 1996-05-08 1999-01-26 Lattice Semiconductor Corporation Method and apparatus for in-system programming of a programmable logic device using a two-wire interface
US6097211A (en) * 1996-07-18 2000-08-01 Altera Corporation Configuration memory integrated circuit
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US6034541A (en) * 1997-04-07 2000-03-07 Lattice Semiconductor Corporation In-system programmable interconnect circuit
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US6262595B1 (en) 1997-06-10 2001-07-17 Altera Corporation High-speed programmable interconnect
JPH1172541A (ja) 1997-06-10 1999-03-16 Altera Corp プログラマブル集積回路を構成する方法、プログラマブル集積回路、jtag回路の使用、およびjtag命令レジスタに入力される命令の使用
US6691267B1 (en) 1997-06-10 2004-02-10 Altera Corporation Technique to test an integrated circuit using fewer pins
US6108807A (en) * 1997-07-28 2000-08-22 Lucent Technologies Inc. Apparatus and method for hybrid pin control of boundary scan applications
US6389321B2 (en) * 1997-11-04 2002-05-14 Lattice Semiconductor Corporation Simultaneous wired and wireless remote in-system programming of multiple remote systems
US6032279A (en) * 1997-11-07 2000-02-29 Atmel Corporation Boundary scan system with address dependent instructions
US6577157B1 (en) * 1997-11-14 2003-06-10 Altera Corporation Fully programmable I/O pin with memory
US5848026A (en) * 1997-12-08 1998-12-08 Atmel Corporation Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration
US6172520B1 (en) 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6023570A (en) * 1998-02-13 2000-02-08 Lattice Semiconductor Corp. Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network
US6304099B1 (en) * 1998-05-21 2001-10-16 Lattice Semiconductor Corporation Method and structure for dynamic in-system programming
US6297666B1 (en) 1998-11-24 2001-10-02 Innovasic, Inc. Fully programmable and configurable application specific integrated circuit
US6357037B1 (en) 1999-01-14 2002-03-12 Xilinx, Inc. Methods to securely configure an FPGA to accept selected macros
US6305005B1 (en) 1999-01-14 2001-10-16 Xilinx, Inc. Methods to securely configure an FPGA using encrypted macros
US6160418A (en) * 1999-01-14 2000-12-12 Xilinx, Inc. Integrated circuit with selectively disabled logic blocks
US6324676B1 (en) 1999-01-14 2001-11-27 Xilinx, Inc. FPGA customizable to accept selected macros
US6301695B1 (en) 1999-01-14 2001-10-09 Xilinx, Inc. Methods to securely configure an FPGA using macro markers
US6654889B1 (en) 1999-02-19 2003-11-25 Xilinx, Inc. Method and apparatus for protecting proprietary configuration data for programmable logic devices
US6697387B1 (en) 1999-06-07 2004-02-24 Micron Technology, Inc. Apparatus for multiplexing signals through I/O pins
US6678287B1 (en) 1999-06-07 2004-01-13 Micron Technology, Inc. Method for multiplexing signals through I/O pins
US6552410B1 (en) 1999-08-31 2003-04-22 Quicklogic Corporation Programmable antifuse interfacing a programmable logic and a dedicated device
TW512467B (en) * 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
US6519753B1 (en) 1999-11-30 2003-02-11 Quicklogic Corporation Programmable device with an embedded portion for receiving a standard circuit design
US7155711B2 (en) * 1999-12-10 2006-12-26 Sedna Patent Services, Llc Method and apparatus providing remote reprogramming of programmable logic devices using embedded JTAG physical layer and protocol
US6642743B2 (en) 2001-02-09 2003-11-04 Stmicroelectronics Ltd. System for rapid configuration of a programmable logic device
US7373515B2 (en) * 2001-10-09 2008-05-13 Wireless Key Identification Systems, Inc. Multi-factor authentication system
US6996713B1 (en) 2002-03-29 2006-02-07 Xilinx, Inc. Method and apparatus for protecting proprietary decryption keys for programmable logic devices
US7162644B1 (en) 2002-03-29 2007-01-09 Xilinx, Inc. Methods and circuits for protecting proprietary configuration data for programmable logic devices
US7191265B1 (en) * 2003-04-29 2007-03-13 Cisco Technology, Inc. JTAG and boundary scan automatic chain selection
US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
US7170315B2 (en) 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7138824B1 (en) 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
US20060080632A1 (en) * 2004-09-30 2006-04-13 Mathstar, Inc. Integrated circuit layout having rectilinear structure of objects
US7099189B1 (en) * 2004-10-05 2006-08-29 Actel Corporation SRAM cell controlled by non-volatile memory cell
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
US7119398B1 (en) 2004-12-22 2006-10-10 Actel Corporation Power-up and power-down circuit for system-on-a-chip integrated circuit
US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
US20070247189A1 (en) * 2005-01-25 2007-10-25 Mathstar Field programmable semiconductor object array integrated circuit
KR101260632B1 (ko) * 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US20070076502A1 (en) * 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US8316158B1 (en) 2007-03-12 2012-11-20 Cypress Semiconductor Corporation Configuration of programmable device using a DMA controller
US8060661B1 (en) 2007-03-27 2011-11-15 Cypress Semiconductor Corporation Interface circuit and method for programming or communicating with an integrated circuit via a power supply pin
US7688652B2 (en) * 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
US20090144595A1 (en) * 2007-11-30 2009-06-04 Mathstar, Inc. Built-in self-testing (bist) of field programmable object arrays
EP2263316A4 (de) * 2008-03-25 2012-10-03 Cochlear Ltd Konfiguration elektronischer komponenten
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices

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US5023484A (en) * 1988-09-02 1991-06-11 Cypress Semiconductor Corporation Architecture of high speed synchronous state machine
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US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
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Also Published As

Publication number Publication date
EP0582660A4 (en) 1994-07-06
DE69221611T2 (de) 1998-02-12
JPH11508093A (ja) 1999-07-13
US5237218A (en) 1993-08-17
WO1992020157A1 (en) 1992-11-12
EP0582660A1 (de) 1994-02-16
DE582660T1 (de) 1994-12-08
JP3507488B2 (ja) 2004-03-15
EP0582660B1 (de) 1997-08-13
US5336951A (en) 1994-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee