DE69222330D1 - Verfahren zum Herstellen einer Halbleitervorrichtung durch stromloses Plattieren - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung durch stromloses Plattieren

Info

Publication number
DE69222330D1
DE69222330D1 DE69222330T DE69222330T DE69222330D1 DE 69222330 D1 DE69222330 D1 DE 69222330D1 DE 69222330 T DE69222330 T DE 69222330T DE 69222330 T DE69222330 T DE 69222330T DE 69222330 D1 DE69222330 D1 DE 69222330D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
electroless plating
electroless
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69222330T
Other languages
English (en)
Other versions
DE69222330T2 (de
Inventor
Andreas M T P Van Der Putten
Johannes W G De Bakker
Johannes M G Rikken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE69222330D1 publication Critical patent/DE69222330D1/de
Application granted granted Critical
Publication of DE69222330T2 publication Critical patent/DE69222330T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/422Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/903Catalyst aided deposition
DE69222330T 1991-02-12 1992-02-05 Verfahren zum Herstellen einer Halbleitervorrichtung durch stromloses Plattieren Expired - Fee Related DE69222330T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9100241A NL9100241A (nl) 1991-02-12 1991-02-12 Werkwijze voor de vervaardiging van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
DE69222330D1 true DE69222330D1 (de) 1997-10-30
DE69222330T2 DE69222330T2 (de) 1998-04-02

Family

ID=19858863

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69222330T Expired - Fee Related DE69222330T2 (de) 1991-02-12 1992-02-05 Verfahren zum Herstellen einer Halbleitervorrichtung durch stromloses Plattieren

Country Status (5)

Country Link
US (1) US5198389A (de)
EP (1) EP0499314B1 (de)
JP (1) JPH04316353A (de)
DE (1) DE69222330T2 (de)
NL (1) NL9100241A (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940010197A (ko) * 1992-10-13 1994-05-24 김광호 반도체 장치의 제조방법
KR960001176B1 (ko) * 1992-12-02 1996-01-19 현대전자산업주식회사 반도체 접속장치 및 그 제조방법
USRE36475E (en) * 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
US5409861A (en) * 1993-09-15 1995-04-25 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
KR100362751B1 (ko) * 1994-01-19 2003-02-11 소니 가부시끼 가이샤 반도체소자의콘택트홀및그형성방법
US5595943A (en) * 1994-06-30 1997-01-21 Hitachi, Ltd. Method for formation of conductor using electroless plating
US5529953A (en) * 1994-10-14 1996-06-25 Toshiba America Electronic Components, Inc. Method of forming studs and interconnects in a multi-layered semiconductor device
US6547974B1 (en) * 1995-06-27 2003-04-15 International Business Machines Corporation Method of producing fine-line circuit boards using chemical polishing
US5891804A (en) * 1996-04-18 1999-04-06 Texas Instruments Incorporated Process for conductors with selective deposition
US6093335A (en) * 1996-08-28 2000-07-25 International Business Machines Corporation Method of surface finishes for eliminating surface irregularities and defects
US6495200B1 (en) * 1998-12-07 2002-12-17 Chartered Semiconductor Manufacturing Ltd. Method to deposit a seeding layer for electroless copper plating
US6368953B1 (en) 2000-05-09 2002-04-09 International Business Machines Corporation Encapsulated metal structures for semiconductor devices and MIM capacitors including the same
US6368484B1 (en) 2000-05-09 2002-04-09 International Business Machines Corporation Selective plating process
JP2002348680A (ja) * 2001-05-22 2002-12-04 Sharp Corp 金属膜パターンおよびその製造方法
KR20190104902A (ko) * 2018-03-02 2019-09-11 마이크로머티어리얼즈 엘엘씨 금속 산화물들을 제거하기 위한 방법들

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293591A (en) * 1975-10-23 1981-10-06 Nathan Feldstein Process using activated electroless plating catalysts
US4268536A (en) * 1978-12-07 1981-05-19 Western Electric Company, Inc. Method for depositing a metal on a surface
DE3380413D1 (en) * 1982-04-27 1989-09-21 Richardson Chemical Co Process for selectively depositing a nickel-boron coating over a metallurgy pattern on a dielectric substrate and products produced thereby
CN1003524B (zh) * 1985-10-14 1989-03-08 株式会社日立制作所 无电浸镀金溶液
JPH01144653A (ja) * 1987-12-01 1989-06-06 Oki Electric Ind Co Ltd 半導体素子の製造方法
NL8900305A (nl) * 1989-02-08 1990-09-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
GB2233820A (en) * 1989-06-26 1991-01-16 Philips Nv Providing an electrode on a semiconductor device
US5112448A (en) * 1989-11-28 1992-05-12 The Boeing Company Self-aligned process for fabrication of interconnect structures in semiconductor applications

Also Published As

Publication number Publication date
EP0499314A2 (de) 1992-08-19
EP0499314B1 (de) 1997-09-24
NL9100241A (nl) 1991-08-01
JPH04316353A (ja) 1992-11-06
US5198389A (en) 1993-03-30
DE69222330T2 (de) 1998-04-02
EP0499314A3 (en) 1993-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee