DE69225082D1 - Halbleiter-Vorrichtung mit Verdrahtung der verbesserten Zuverlässigkeit und Verfahren zu ihner Herstellung - Google Patents
Halbleiter-Vorrichtung mit Verdrahtung der verbesserten Zuverlässigkeit und Verfahren zu ihner HerstellungInfo
- Publication number
- DE69225082D1 DE69225082D1 DE69225082T DE69225082T DE69225082D1 DE 69225082 D1 DE69225082 D1 DE 69225082D1 DE 69225082 T DE69225082 T DE 69225082T DE 69225082 T DE69225082 T DE 69225082T DE 69225082 D1 DE69225082 D1 DE 69225082D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- semiconductor device
- improved reliability
- reliability wiring
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1864291 | 1991-02-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69225082D1 true DE69225082D1 (de) | 1998-05-20 |
DE69225082T2 DE69225082T2 (de) | 1998-08-20 |
Family
ID=11977259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69225082T Expired - Fee Related DE69225082T2 (de) | 1991-02-12 | 1992-02-10 | Halbleiter-Vorrichtung mit Verdrahtung der verbesserten Zuverlässigkeit und Verfahren zu ihner Herstellung |
Country Status (3)
Country | Link |
---|---|
US (2) | US5459353A (de) |
EP (1) | EP0499433B1 (de) |
DE (1) | DE69225082T2 (de) |
Families Citing this family (58)
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JPH05315332A (ja) * | 1992-04-02 | 1993-11-26 | Nec Corp | 半導体装置およびその製造方法 |
JPH06140396A (ja) * | 1992-10-23 | 1994-05-20 | Yamaha Corp | 半導体装置とその製法 |
JP3587537B2 (ja) * | 1992-12-09 | 2004-11-10 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US5635763A (en) * | 1993-03-22 | 1997-06-03 | Sanyo Electric Co., Ltd. | Semiconductor device having cap-metal layer |
DE19515564B4 (de) | 1994-04-28 | 2008-07-03 | Denso Corp., Kariya | Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben |
EP0690503A1 (de) * | 1994-05-31 | 1996-01-03 | Advanced Micro Devices, Inc. | Verbesserte Struktur einer Verbindungsleitung und Verfahren dafür |
US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
US5702979A (en) * | 1994-05-31 | 1997-12-30 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
US5956615A (en) * | 1994-05-31 | 1999-09-21 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
EP0697723A3 (de) * | 1994-08-15 | 1997-04-16 | Ibm | Verfahren zur Metallisierung einer isolierenden Schicht |
US5705427A (en) * | 1994-12-22 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
JP4156044B2 (ja) * | 1994-12-22 | 2008-09-24 | エスティーマイクロエレクトロニクス,インコーポレイテッド | 集積回路におけるランディングパッド構成体の製造方法 |
JPH08176823A (ja) * | 1994-12-26 | 1996-07-09 | Sony Corp | 高融点金属薄膜の成膜方法 |
US5639691A (en) * | 1995-06-05 | 1997-06-17 | Advanced Micro Devices, Inc. | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device |
KR100220933B1 (ko) * | 1995-06-30 | 1999-09-15 | 김영환 | 반도체 소자의 금속배선 형성방법 |
US5831283A (en) | 1995-11-30 | 1998-11-03 | International Business Machines Corporation | Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD |
US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
US5849635A (en) * | 1996-07-11 | 1998-12-15 | Micron Technology, Inc. | Semiconductor processing method of forming an insulating dielectric layer and a contact opening therein |
US5990513A (en) | 1996-10-08 | 1999-11-23 | Ramtron International Corporation | Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion |
US6071810A (en) * | 1996-12-24 | 2000-06-06 | Kabushiki Kaisha Toshiba | Method of filling contact holes and wiring grooves of a semiconductor device |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
US6395629B1 (en) * | 1997-04-16 | 2002-05-28 | Stmicroelectronics, Inc. | Interconnect method and structure for semiconductor devices |
US5920081A (en) * | 1997-04-25 | 1999-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure of a bond pad to prevent testing probe pin contamination |
TW451450B (en) * | 1997-04-28 | 2001-08-21 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device with a multilayer wiring |
TW396454B (en) | 1997-06-24 | 2000-07-01 | Matsushita Electrics Corporati | Semiconductor device and method for fabricating the same |
TW408433B (en) * | 1997-06-30 | 2000-10-11 | Hitachi Ltd | Method for fabricating semiconductor integrated circuit |
JP3456391B2 (ja) * | 1997-07-03 | 2003-10-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US5976976A (en) | 1997-08-21 | 1999-11-02 | Micron Technology, Inc. | Method of forming titanium silicide and titanium by chemical vapor deposition |
US6136677A (en) * | 1997-09-25 | 2000-10-24 | Siemens Aktiengesellschaft | Method of fabricating semiconductor chips with silicide and implanted junctions |
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JP3424900B2 (ja) * | 1997-10-24 | 2003-07-07 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US5994211A (en) * | 1997-11-21 | 1999-11-30 | Lsi Logic Corporation | Method and composition for reducing gate oxide damage during RF sputter clean |
US6284316B1 (en) | 1998-02-25 | 2001-09-04 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
US6143362A (en) * | 1998-02-25 | 2000-11-07 | Micron Technology, Inc. | Chemical vapor deposition of titanium |
JP2000114370A (ja) * | 1998-10-06 | 2000-04-21 | Oki Electric Ind Co Ltd | 半導体装置 |
US6936531B2 (en) * | 1998-12-21 | 2005-08-30 | Megic Corporation | Process of fabricating a chip structure |
JP3533968B2 (ja) | 1998-12-22 | 2004-06-07 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2000315687A (ja) * | 1999-04-30 | 2000-11-14 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2001060590A (ja) | 1999-08-20 | 2001-03-06 | Denso Corp | 半導体装置の電気配線及びその製造方法 |
US6225219B1 (en) * | 1999-12-20 | 2001-05-01 | United Microelectronics Corp. | Method of stabilizing anti-reflection coating layer |
US6668445B1 (en) * | 2000-01-11 | 2003-12-30 | Lexmark International, Inc. | Method of increasing tab bond strength using reactive ion etching |
JP3449333B2 (ja) | 2000-03-27 | 2003-09-22 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP3480416B2 (ja) | 2000-03-27 | 2003-12-22 | セイコーエプソン株式会社 | 半導体装置 |
JP3676185B2 (ja) * | 2000-04-14 | 2005-07-27 | シャープ株式会社 | 半導体装置 |
US6441490B1 (en) * | 2000-12-18 | 2002-08-27 | Advanced Micro Devices, Inc. | Low dielectric constant stop layer for integrated circuit interconnects |
US6794705B2 (en) * | 2000-12-28 | 2004-09-21 | Infineon Technologies Ag | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials |
US20020096744A1 (en) * | 2001-01-24 | 2002-07-25 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in integrated circuits |
JP2003177482A (ja) * | 2001-12-12 | 2003-06-27 | Sony Corp | 光学読み取り用原稿台および光学読み取り装置 |
US7932603B2 (en) | 2001-12-13 | 2011-04-26 | Megica Corporation | Chip structure and process for forming the same |
US6777328B2 (en) * | 2002-01-31 | 2004-08-17 | Oki Electric Industry Co., Ltd. | Method of forming multilayered conductive layers for semiconductor device |
US20040203230A1 (en) * | 2002-01-31 | 2004-10-14 | Tetsuo Usami | Semiconductor device having multilayered conductive layers |
US7122903B2 (en) * | 2003-10-21 | 2006-10-17 | Sharp Kabushiki Kaisha | Contact plug processing and a contact plug |
US9092582B2 (en) | 2010-07-09 | 2015-07-28 | Cypress Semiconductor Corporation | Low power, low pin count interface for an RFID transponder |
US8723654B2 (en) | 2010-07-09 | 2014-05-13 | Cypress Semiconductor Corporation | Interrupt generation and acknowledgment for RFID |
US9846664B2 (en) | 2010-07-09 | 2017-12-19 | Cypress Semiconductor Corporation | RFID interface and interrupt |
US11004685B2 (en) * | 2018-11-30 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer structures and methods of forming |
US20210020455A1 (en) * | 2019-07-17 | 2021-01-21 | Nanya Technology Corporation | Conductive via structure |
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JPS57208161A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Semiconductor device |
US4357203A (en) * | 1981-12-30 | 1982-11-02 | Rca Corporation | Plasma etching of polyimide |
JPS58137231A (ja) * | 1982-02-09 | 1983-08-15 | Nec Corp | 集積回路装置 |
JPS605560A (ja) * | 1983-06-23 | 1985-01-12 | Fujitsu Ltd | 半導体装置 |
US4999318A (en) * | 1986-11-12 | 1991-03-12 | Hitachi, Ltd. | Method for forming metal layer interconnects using stepped via walls |
US4924295A (en) * | 1986-11-28 | 1990-05-08 | Siemens Aktiengesellschaft | Integrated semi-conductor circuit comprising at least two metallization levels composed of aluminum or aluminum compounds and a method for the manufacture of same |
US4910580A (en) * | 1987-08-27 | 1990-03-20 | Siemens Aktiengesellschaft | Method for manufacturing a low-impedance, planar metallization composed of aluminum or of an aluminum alloy |
JPH01241149A (ja) * | 1988-03-23 | 1989-09-26 | Seiko Epson Corp | 半導体装置 |
JPH01266746A (ja) * | 1988-04-18 | 1989-10-24 | Sony Corp | 半導体装置 |
FR2634317A1 (fr) * | 1988-07-12 | 1990-01-19 | Philips Nv | Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions |
JPH0271631A (ja) * | 1988-09-07 | 1990-03-12 | Fujitsu Ltd | 雑音量検出回路 |
US4942451A (en) * | 1988-09-27 | 1990-07-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having improved antireflection coating |
JPH02122653A (ja) * | 1988-11-01 | 1990-05-10 | Oki Electric Ind Co Ltd | 半導体素子用層間膜 |
NL8900010A (nl) * | 1989-01-04 | 1990-08-01 | Philips Nv | Halfgeleiderinrichting en werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
JPH02235372A (ja) * | 1989-03-08 | 1990-09-18 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
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US5108951A (en) * | 1990-11-05 | 1992-04-28 | Sgs-Thomson Microelectronics, Inc. | Method for forming a metal contact |
US5094981A (en) * | 1990-04-17 | 1992-03-10 | North American Philips Corporation, Signetics Div. | Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C. |
US5117273A (en) * | 1990-11-16 | 1992-05-26 | Sgs-Thomson Microelectronics, Inc. | Contact for integrated circuits |
US5136362A (en) * | 1990-11-27 | 1992-08-04 | Grief Malcolm K | Electrical contact with diffusion barrier |
US5225372A (en) * | 1990-12-24 | 1993-07-06 | Motorola, Inc. | Method of making a semiconductor device having an improved metallization structure |
JP2660359B2 (ja) * | 1991-01-30 | 1997-10-08 | 三菱電機株式会社 | 半導体装置 |
JP2655213B2 (ja) * | 1991-10-14 | 1997-09-17 | 三菱電機株式会社 | 半導体装置の配線接続構造およびその製造方法 |
US5290588A (en) * | 1991-12-19 | 1994-03-01 | Advanced Micro Devices, Incorporated | TiW barrier metal process |
US5240880A (en) * | 1992-05-05 | 1993-08-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5356836A (en) * | 1993-08-19 | 1994-10-18 | Industrial Technology Research Institute | Aluminum plug process |
-
1992
- 1992-02-10 DE DE69225082T patent/DE69225082T2/de not_active Expired - Fee Related
- 1992-02-10 EP EP92301098A patent/EP0499433B1/de not_active Expired - Lifetime
-
1995
- 1995-01-05 US US08/369,253 patent/US5459353A/en not_active Expired - Lifetime
-
1996
- 1996-06-06 US US08/660,745 patent/US5712194A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0499433B1 (de) | 1998-04-15 |
US5712194A (en) | 1998-01-27 |
US5459353A (en) | 1995-10-17 |
DE69225082T2 (de) | 1998-08-20 |
EP0499433A3 (en) | 1993-10-27 |
EP0499433A2 (de) | 1992-08-19 |
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