DE69225520D1 - Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur - Google Patents

Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur

Info

Publication number
DE69225520D1
DE69225520D1 DE69225520T DE69225520T DE69225520D1 DE 69225520 D1 DE69225520 D1 DE 69225520D1 DE 69225520 T DE69225520 T DE 69225520T DE 69225520 T DE69225520 T DE 69225520T DE 69225520 D1 DE69225520 D1 DE 69225520D1
Authority
DE
Germany
Prior art keywords
mismatched
object including
semiconductor heterostructure
lattice layers
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69225520T
Other languages
English (en)
Other versions
DE69225520T2 (de
Inventor
John Condon Bean
Gregg Sumio Higashi
Robert Hull
Justin Larry Peticolas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69225520D1 publication Critical patent/DE69225520D1/de
Publication of DE69225520T2 publication Critical patent/DE69225520T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
DE69225520T 1991-03-18 1992-03-12 Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur Expired - Lifetime DE69225520T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/671,276 US5091767A (en) 1991-03-18 1991-03-18 Article comprising a lattice-mismatched semiconductor heterostructure

Publications (2)

Publication Number Publication Date
DE69225520D1 true DE69225520D1 (de) 1998-06-25
DE69225520T2 DE69225520T2 (de) 1998-10-01

Family

ID=24693839

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225520T Expired - Lifetime DE69225520T2 (de) 1991-03-18 1992-03-12 Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur

Country Status (4)

Country Link
US (1) US5091767A (de)
EP (1) EP0505093B1 (de)
JP (1) JP3027473B2 (de)
DE (1) DE69225520T2 (de)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19604348C2 (de) * 1996-02-07 2003-10-23 Deutsche Telekom Ag Verfahren zur Herstellung einer kalibrierten Längenskala im Nanometerbereich für technische Geräte, die der hochauflösenden bis ultrahochauflösenden Abbildung von Strukturen dienen
US5719895A (en) * 1996-09-25 1998-02-17 Picolight Incorporated Extended wavelength strained layer lasers having short period superlattices
US5719894A (en) * 1996-09-25 1998-02-17 Picolight Incorporated Extended wavelength strained layer lasers having nitrogen disposed therein
US5825796A (en) * 1996-09-25 1998-10-20 Picolight Incorporated Extended wavelength strained layer lasers having strain compensated layers
JP2930032B2 (ja) * 1996-09-26 1999-08-03 日本電気株式会社 Ｉｉ−ｖｉ族化合物半導体発光素子およびその製造方法
US5859864A (en) * 1996-10-28 1999-01-12 Picolight Incorporated Extended wavelength lasers having a restricted growth surface and graded lattice mismatch
US5877519A (en) * 1997-03-26 1999-03-02 Picolight Incoporated Extended wavelength opto-electronic devices
DE19720008A1 (de) * 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
KR100400808B1 (ko) * 1997-06-24 2003-10-08 매사츄세츠 인스티튜트 오브 테크놀러지 그레이드된 ＧｅＳｉ층 및 평탄화를 사용한 Ｓｉ상의 Ｇｅ의 쓰레딩 전위 밀도 제어
WO1999019546A1 (en) 1997-10-10 1999-04-22 Cornell Research Foundation, Inc. Methods for growing defect-free heteroepitaxial layers
JP2001506062A (ja) * 1997-10-14 2001-05-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 低温ｃｖｄによる半導体装置の製造方法
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6087683A (en) * 1998-07-31 2000-07-11 Lucent Technologies Silicon germanium heterostructure bipolar transistor with indium doped base
US6335546B1 (en) * 1998-07-31 2002-01-01 Sharp Kabushiki Kaisha Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device
JP3201475B2 (ja) * 1998-09-14 2001-08-20 松下電器産業株式会社 半導体装置およびその製造方法
US6635110B1 (en) 1999-06-25 2003-10-21 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
US6821805B1 (en) * 1999-10-06 2004-11-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device, semiconductor substrate, and manufacture method
WO2001054175A1 (en) * 2000-01-20 2001-07-26 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6589335B2 (en) * 2001-02-08 2003-07-08 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
US6784074B2 (en) * 2001-05-09 2004-08-31 Nsc-Nanosemiconductor Gmbh Defect-free semiconductor templates for epitaxial growth and method of making same
US6653166B2 (en) 2001-05-09 2003-11-25 Nsc-Nanosemiconductor Gmbh Semiconductor device and method of making same
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6946371B2 (en) * 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US20040115916A1 (en) * 2002-07-29 2004-06-17 Amberwave Systems Corporation Selective placement of dislocation arrays
EP1530800B1 (de) * 2002-08-23 2016-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-heterostrukturen mit reduzierter anhäufung von versetzungen und entsprechende herstellungsverfahren
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
EP2337062A3 (de) * 2003-01-27 2016-05-04 Taiwan Semiconductor Manufacturing Company, Limited Herstellungsverfahren von HALBLEITERSTRUKTUREN MIT STRUKTURHOMOGENITÄT
CN100437970C (zh) * 2003-03-07 2008-11-26 琥珀波系统公司 一种结构及用于形成半导体结构的方法
GB2418531A (en) * 2004-09-22 2006-03-29 Univ Warwick Formation of lattice-tuning semiconductor substrates
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
FI20045482A0 (fi) 2004-12-14 2004-12-14 Optogan Oy Matalamman dislokaatiotiheyden omaava puolijohdesubstraatti, ja menetelmä sen valmistamiseksi
DE102005000826A1 (de) * 2005-01-05 2006-07-20 Siltronic Ag Halbleiterscheibe mit Silicium-Germanium-Schicht und Verfahren zu deren Herstellung
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
WO2006125040A2 (en) * 2005-05-17 2006-11-23 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
WO2007014294A2 (en) * 2005-07-26 2007-02-01 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
WO2007112066A2 (en) * 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
US7875958B2 (en) * 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US7825328B2 (en) * 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) * 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) * 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8304805B2 (en) * 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
DE112008002387B4 (de) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Struktur einer Mehrfachübergangs-Solarzelle, Verfahren zur Bildung einer photonischenVorrichtung, Photovoltaische Mehrfachübergangs-Zelle und Photovoltaische Mehrfachübergangs-Zellenvorrichtung,
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8138066B2 (en) * 2008-10-01 2012-03-20 International Business Machines Corporation Dislocation engineering using a scanned laser
CN102379046B (zh) * 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
KR101643021B1 (ko) * 2009-06-05 2016-07-26 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 반도체 기판, 광전 변환 디바이스, 반도체 기판의 제조 방법 및 광전 변환 디바이스의 제조 방법
TWI562195B (en) 2010-04-27 2016-12-11 Pilegrowth Tech S R L Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
RU2586009C1 (ru) * 2014-12-10 2016-06-10 федеральное государственное бюджетное образовательное учреждение высшего образования Кабардино-Балкарский государственный университет им. Х.М. Бербекова Способ изготовления полупроводниковой структуры

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4632712A (en) * 1983-09-12 1986-12-30 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US4707216A (en) * 1986-01-24 1987-11-17 University Of Illinois Semiconductor deposition method and device
US4872046A (en) * 1986-01-24 1989-10-03 University Of Illinois Heterojunction semiconductor device with <001> tilt
GB2215514A (en) * 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5032893A (en) * 1988-04-01 1991-07-16 Cornell Research Foundation, Inc. Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers
JPH039515A (ja) * 1989-06-07 1991-01-17 Sharp Corp 半導体装置

Also Published As

Publication number Publication date
JPH04318918A (ja) 1992-11-10
JP3027473B2 (ja) 2000-04-04
US5091767A (en) 1992-02-25
DE69225520T2 (de) 1998-10-01
EP0505093A2 (de) 1992-09-23
EP0505093B1 (de) 1998-05-20
EP0505093A3 (en) 1994-06-22

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