DE69229090D1 - Integrierte Halbleiterschaltungsanordnung mit Möglichkeit, die Produktspezifikation zu ändern - Google Patents

Integrierte Halbleiterschaltungsanordnung mit Möglichkeit, die Produktspezifikation zu ändern

Info

Publication number
DE69229090D1
DE69229090D1 DE69229090T DE69229090T DE69229090D1 DE 69229090 D1 DE69229090 D1 DE 69229090D1 DE 69229090 T DE69229090 T DE 69229090T DE 69229090 T DE69229090 T DE 69229090T DE 69229090 D1 DE69229090 D1 DE 69229090D1
Authority
DE
Germany
Prior art keywords
possibility
changing
circuit arrangement
semiconductor circuit
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69229090T
Other languages
English (en)
Other versions
DE69229090T2 (de
Inventor
Kenji Numata
Masaki Ogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69229090D1 publication Critical patent/DE69229090D1/de
Application granted granted Critical
Publication of DE69229090T2 publication Critical patent/DE69229090T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
DE69229090T 1991-08-30 1992-08-28 Integrierte Halbleiterschaltungsanordnung mit Möglichkeit, die Produktspezifikation zu ändern Expired - Lifetime DE69229090T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21992691 1991-08-30
JP22169492A JP3776461B2 (ja) 1991-08-30 1992-08-20 半導体集積回路装置およびチップ選別方法

Publications (2)

Publication Number Publication Date
DE69229090D1 true DE69229090D1 (de) 1999-06-10
DE69229090T2 DE69229090T2 (de) 1999-10-14

Family

ID=26523412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229090T Expired - Lifetime DE69229090T2 (de) 1991-08-30 1992-08-28 Integrierte Halbleiterschaltungsanordnung mit Möglichkeit, die Produktspezifikation zu ändern

Country Status (4)

Country Link
US (5) US5633827A (de)
EP (1) EP0530714B1 (de)
JP (1) JP3776461B2 (de)
DE (1) DE69229090T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3776461B2 (ja) * 1991-08-30 2006-05-17 株式会社東芝 半導体集積回路装置およびチップ選別方法
JP3090833B2 (ja) * 1993-12-28 2000-09-25 株式会社東芝 半導体記憶装置
JP3723615B2 (ja) * 1995-01-06 2005-12-07 株式会社ルネサステクノロジ ダイナミック型半導体記憶装置
KR0145888B1 (ko) * 1995-04-13 1998-11-02 김광호 반도체 메모리장치의 동작 모드 전환회로
US6026044A (en) * 1997-06-30 2000-02-15 Townsend & Townsend & Crew Llp High speed video frame buffer
US6031783A (en) * 1996-08-09 2000-02-29 Townsend And Townsend And Crew Llp High speed video frame buffer
US6947100B1 (en) 1996-08-09 2005-09-20 Robert J. Proebsting High speed video frame buffer
TW419828B (en) * 1997-02-26 2001-01-21 Toshiba Corp Semiconductor integrated circuit
US5995437A (en) * 1997-06-02 1999-11-30 Townsend And Townsend And Crew Llp Semiconductor memory and method of accessing memory arrays
US6167544A (en) * 1998-08-19 2000-12-26 Stmicroelectronics, Inc. Method and apparatus for testing dynamic random access memory
JP3184156B2 (ja) * 1998-09-02 2001-07-09 日本電気アイシーマイコンシステム株式会社 半導体集積回路およびその製品仕様制御方法
KR100336838B1 (ko) * 1999-06-17 2002-05-16 윤종용 리프레시 주기 선택 회로 및 입/출력 비트 폭 선택 회로를 구비한 다이내믹 랜덤 액세스 메모리 장치
JP3821621B2 (ja) 1999-11-09 2006-09-13 株式会社東芝 半導体集積回路
US7173867B2 (en) * 2001-02-02 2007-02-06 Broadcom Corporation Memory redundancy circuit techniques
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
JP2002157880A (ja) * 2000-11-15 2002-05-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
JP4534141B2 (ja) * 2005-02-09 2010-09-01 エルピーダメモリ株式会社 半導体記憶装置
US7443735B2 (en) * 2006-12-22 2008-10-28 Sandisk Corporation Method of reducing wordline recovery time
US7495992B2 (en) * 2006-12-22 2009-02-24 Sandisk Corporation System for reducing wordline recovery time
KR100956783B1 (ko) * 2008-10-14 2010-05-12 주식회사 하이닉스반도체 반도체 메모리 장치
US8300489B2 (en) * 2010-01-12 2012-10-30 International Business Machines Corporation Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump
KR101861647B1 (ko) 2011-05-24 2018-05-28 삼성전자주식회사 메모리 시스템 및 그 리프레시 제어 방법
KR20210006616A (ko) 2019-07-09 2021-01-19 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0612609B2 (ja) * 1987-03-27 1994-02-16 株式会社東芝 半導体メモリ
JPH0793003B2 (ja) * 1988-09-01 1995-10-09 三菱電機株式会社 ダイナミックランダムアクセスメモリ装置およびその動作方法
US4933907A (en) * 1987-12-03 1990-06-12 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device and operating method therefor
KR910003593B1 (ko) * 1987-12-30 1991-06-07 삼성전자 주식회사 고집적도 메모리용 모드 선택회로
US5023843A (en) * 1988-10-27 1991-06-11 Texas Instruments Incorporated Bonding pad programmable integrated circuit
JPH02247892A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd ダイナミックランダムアクセスメモリ
JP2928263B2 (ja) * 1989-03-20 1999-08-03 株式会社日立製作所 半導体装置
JPH0760413B2 (ja) * 1989-05-12 1995-06-28 インターナショナル・ビジネス・マシーンズ・コーポレーション メモリ・システム
EP0476282A3 (en) * 1990-07-31 1992-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuits
JP2794138B2 (ja) * 1991-08-13 1998-09-03 三菱電機株式会社 半導体記憶装置
JP3776461B2 (ja) * 1991-08-30 2006-05-17 株式会社東芝 半導体集積回路装置およびチップ選別方法

Also Published As

Publication number Publication date
US5559748A (en) 1996-09-24
US5812481A (en) 1998-09-22
US5633827A (en) 1997-05-27
JPH05234368A (ja) 1993-09-10
US5970015A (en) 1999-10-19
DE69229090T2 (de) 1999-10-14
EP0530714A3 (en) 1994-12-28
JP3776461B2 (ja) 2006-05-17
US6141288A (en) 2000-10-31
EP0530714A2 (de) 1993-03-10
EP0530714B1 (de) 1999-05-06

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