DE69229467D1 - Nichtflüchtige Halbleiterspeicheranordnung mit über den entsprechend verknüpften Auswahltransistoren gestapelten Dünnschichtspeichertransistoren - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung mit über den entsprechend verknüpften Auswahltransistoren gestapelten Dünnschichtspeichertransistoren

Info

Publication number
DE69229467D1
DE69229467D1 DE69229467T DE69229467T DE69229467D1 DE 69229467 D1 DE69229467 D1 DE 69229467D1 DE 69229467 T DE69229467 T DE 69229467T DE 69229467 T DE69229467 T DE 69229467T DE 69229467 D1 DE69229467 D1 DE 69229467D1
Authority
DE
Germany
Prior art keywords
transistors
thin
volatile semiconductor
stacked over
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229467T
Other languages
English (en)
Other versions
DE69229467T2 (de
Inventor
Shoji Koyama
Tatsuro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP03337636A external-priority patent/JP3060680B2/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69229467D1 publication Critical patent/DE69229467D1/de
Application granted granted Critical
Publication of DE69229467T2 publication Critical patent/DE69229467T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
DE69229467T 1991-11-26 1992-11-23 Nichtflüchtige Halbleiterspeicheranordnung mit über den entsprechend verknüpften Auswahltransistoren gestapelten Dünnschichtspeichertransistoren Expired - Fee Related DE69229467T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03337636A JP3060680B2 (ja) 1990-11-30 1991-11-26 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69229467D1 true DE69229467D1 (de) 1999-07-29
DE69229467T2 DE69229467T2 (de) 2000-01-20

Family

ID=18310524

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229467T Expired - Fee Related DE69229467T2 (de) 1991-11-26 1992-11-23 Nichtflüchtige Halbleiterspeicheranordnung mit über den entsprechend verknüpften Auswahltransistoren gestapelten Dünnschichtspeichertransistoren

Country Status (3)

Country Link
US (1) US5321286A (de)
EP (1) EP0544204B1 (de)
DE (1) DE69229467T2 (de)

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JP3224907B2 (ja) * 1993-06-08 2001-11-05 株式会社東芝 不揮発性半導体記憶装置
KR0135166B1 (ko) * 1993-07-20 1998-04-25 문정환 반도체장치의 게이트 형성방법
JP3192861B2 (ja) * 1994-03-14 2001-07-30 株式会社東芝 不揮発性半導体記憶装置
US5488579A (en) * 1994-04-29 1996-01-30 Motorola Inc. Three-dimensionally integrated nonvolatile SRAM cell and process
US5452250A (en) * 1994-06-14 1995-09-19 International Business Machines, Inc. Non-volatile register system utilizing thin-film floating-gate amorphous transistors
JP2689921B2 (ja) * 1994-09-29 1997-12-10 日本電気株式会社 半導体不揮発性記憶装置及びその製造方法
US5889302A (en) * 1997-04-21 1999-03-30 Advanced Micro Devices, Inc. Multilayer floating gate field effect transistor structure for use in integrated circuit devices
US6849557B1 (en) 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
JPH11143379A (ja) * 1997-09-03 1999-05-28 Semiconductor Energy Lab Co Ltd 半導体表示装置補正システムおよび半導体表示装置の補正方法
US6022770A (en) * 1998-03-24 2000-02-08 International Business Machines Corporation NVRAM utilizing high voltage TFT device and method for making the same
US6277758B1 (en) 1998-07-23 2001-08-21 Micron Technology, Inc. Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
US6215130B1 (en) * 1998-08-20 2001-04-10 Lucent Technologies Inc. Thin film transistors
WO2000041236A1 (en) * 1999-01-06 2000-07-13 Advanced Micro Devices, Inc. Integrated circuit memory cell upon a dielectric base
US6259133B1 (en) 1999-02-11 2001-07-10 Advanced Micro Devices, Inc. Method for forming an integrated circuit memory cell and product thereof
US6272047B1 (en) * 1999-12-17 2001-08-07 Micron Technology, Inc. Flash memory cell
US6320228B1 (en) 2000-01-14 2001-11-20 Advanced Micro Devices, Inc. Multiple active layer integrated circuit and a method of making such a circuit
US6225646B1 (en) * 2000-01-14 2001-05-01 Advanced Micro Devices, Inc. Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
US6888750B2 (en) * 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US6743680B1 (en) 2000-06-22 2004-06-01 Advanced Micro Devices, Inc. Process for manufacturing transistors having silicon/germanium channel regions
US6429484B1 (en) 2000-08-07 2002-08-06 Advanced Micro Devices, Inc. Multiple active layer structure and a method of making such a structure
EP2988331B1 (de) 2000-08-14 2019-01-09 SanDisk Technologies LLC Halbleiterspeicherbauelement
US6709935B1 (en) 2001-03-26 2004-03-23 Advanced Micro Devices, Inc. Method of locally forming a silicon/geranium channel layer
US6522584B1 (en) * 2001-08-02 2003-02-18 Micron Technology, Inc. Programming methods for multi-level flash EEPROMs
US6593624B2 (en) 2001-09-25 2003-07-15 Matrix Semiconductor, Inc. Thin film transistors with vertically offset drain regions
US6841813B2 (en) * 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
US6989108B2 (en) * 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition
KR100466187B1 (ko) * 2002-05-17 2005-01-13 주식회사 하이닉스반도체 플래시 메모리 셀
US20060203541A1 (en) 2003-03-18 2006-09-14 Haruki Toda Phase change memory device
DE60306893T2 (de) * 2003-05-07 2007-02-01 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung einer elektrischen Speichereinrichtung mit Auswahltransistoren für Speicherelemente sowie entsprechend hergestellte Speichereinrichtung
JP2005223102A (ja) * 2004-02-04 2005-08-18 Nec Corp 不揮発性記憶装置及びその製造方法
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
JP4445299B2 (ja) * 2004-03-18 2010-04-07 富士通株式会社 不揮発性メモリ評価方法
EP1768554A4 (de) * 2004-07-16 2010-12-08 Semiconductor Energy Lab Biologische signalverarbeitungseinheit, drahtloses gedächtnis, biologisches signalverarbeitungssystem und kontrollsystem für die zu steuernde vorrichtung
KR100673019B1 (ko) * 2005-12-12 2007-01-24 삼성전자주식회사 적층 구조를 가지는 낸드형 비휘발성 메모리 장치, 그 형성방법 및 동작 방법
US7692223B2 (en) * 2006-04-28 2010-04-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same
KR100850508B1 (ko) * 2006-08-04 2008-08-05 삼성전자주식회사 3차원적으로 배열된 메모리 셀 트랜지스터들을 구비하는낸드 플래시 메모리 장치
KR100806339B1 (ko) * 2006-10-11 2008-02-27 삼성전자주식회사 3차원적으로 배열된 메모리 셀들을 구비하는 낸드 플래시메모리 장치 및 그 제조 방법
KR100886429B1 (ko) * 2007-05-14 2009-03-02 삼성전자주식회사 반도체 소자 및 제조방법
US8542549B2 (en) 2011-08-08 2013-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse bit cell
US8760955B2 (en) * 2011-10-21 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse memory arrays
KR102021808B1 (ko) * 2012-12-04 2019-09-17 삼성전자주식회사 3차원 구조의 메모리 셀 어레이를 포함하는 불휘발성 메모리
US9627395B2 (en) 2015-02-11 2017-04-18 Sandisk Technologies Llc Enhanced channel mobility three-dimensional memory structure and method of making thereof
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof
US10896912B2 (en) 2019-03-20 2021-01-19 International Business Machines Corporation Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices

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Also Published As

Publication number Publication date
EP0544204B1 (de) 1999-06-23
EP0544204A1 (de) 1993-06-02
US5321286A (en) 1994-06-14
DE69229467T2 (de) 2000-01-20

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee