DE69231933D1 - Programmierbare logische zelle und programmierbares logisches feld - Google Patents

Programmierbare logische zelle und programmierbares logisches feld

Info

Publication number
DE69231933D1
DE69231933D1 DE69231933T DE69231933T DE69231933D1 DE 69231933 D1 DE69231933 D1 DE 69231933D1 DE 69231933 T DE69231933 T DE 69231933T DE 69231933 T DE69231933 T DE 69231933T DE 69231933 D1 DE69231933 D1 DE 69231933D1
Authority
DE
Germany
Prior art keywords
cell
functions
improved
core
nearest neighbors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69231933T
Other languages
English (en)
Other versions
DE69231933T2 (de
Inventor
C Furtek
C Camarota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of DE69231933D1 publication Critical patent/DE69231933D1/de
Application granted granted Critical
Publication of DE69231933T2 publication Critical patent/DE69231933T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
DE69231933T 1991-08-30 1992-08-28 Programmierbare logische zelle und programmierbares logisches feld Expired - Lifetime DE69231933T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/752,419 US5245227A (en) 1990-11-02 1991-08-30 Versatile programmable logic cell for use in configurable logic arrays
PCT/US1992/007376 WO1993005577A1 (en) 1991-08-30 1992-08-28 Programme logic cell and array

Publications (2)

Publication Number Publication Date
DE69231933D1 true DE69231933D1 (de) 2001-08-16
DE69231933T2 DE69231933T2 (de) 2002-04-04

Family

ID=25026251

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231933T Expired - Lifetime DE69231933T2 (de) 1991-08-30 1992-08-28 Programmierbare logische zelle und programmierbares logisches feld

Country Status (9)

Country Link
US (1) US5245227A (de)
EP (1) EP0601094B1 (de)
JP (2) JP3432220B2 (de)
KR (1) KR100246903B1 (de)
AT (1) ATE203131T1 (de)
CA (1) CA2116332C (de)
DE (1) DE69231933T2 (de)
SG (1) SG49817A1 (de)
WO (1) WO1993005577A1 (de)

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US6069488A (en) * 1997-11-14 2000-05-30 Xilinx, Inc. Programmable logic device with versatile exclusive or architecture
US6407576B1 (en) 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
JP2003505753A (ja) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
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Also Published As

Publication number Publication date
JP3432220B2 (ja) 2003-08-04
CA2116332C (en) 2001-12-11
KR100246903B1 (ko) 2000-03-15
EP0601094B1 (de) 2001-07-11
SG49817A1 (en) 1998-06-15
JPH06510175A (ja) 1994-11-10
ATE203131T1 (de) 2001-07-15
EP0601094A4 (de) 1995-03-15
DE69231933T2 (de) 2002-04-04
CA2116332A1 (en) 1993-03-18
EP0601094A1 (de) 1994-06-15
WO1993005577A1 (en) 1993-03-18
JP2003152529A (ja) 2003-05-23
JP3474878B2 (ja) 2003-12-08
US5245227A (en) 1993-09-14

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