DE69232749T2 - Verfahren zur Herstellung von defektfreiem Silizium auf einem isolierenden Substrat - Google Patents
Verfahren zur Herstellung von defektfreiem Silizium auf einem isolierenden SubstratInfo
- Publication number
- DE69232749T2 DE69232749T2 DE69232749T DE69232749T DE69232749T2 DE 69232749 T2 DE69232749 T2 DE 69232749T2 DE 69232749 T DE69232749 T DE 69232749T DE 69232749 T DE69232749 T DE 69232749T DE 69232749 T2 DE69232749 T2 DE 69232749T2
- Authority
- DE
- Germany
- Prior art keywords
- insulating substrate
- free silicon
- producing defect
- defect
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US72309191A | 1991-06-28 | 1991-06-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69232749D1 DE69232749D1 (de) | 2002-10-02 |
| DE69232749T2 true DE69232749T2 (de) | 2003-08-07 |
Family
ID=24904800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69232749T Expired - Lifetime DE69232749T2 (de) | 1991-06-28 | 1992-06-03 | Verfahren zur Herstellung von defektfreiem Silizium auf einem isolierenden Substrat |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US5540785A (de) |
| EP (1) | EP0520216B1 (de) |
| JP (1) | JPH07187892A (de) |
| DE (1) | DE69232749T2 (de) |
Families Citing this family (62)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5344524A (en) * | 1993-06-30 | 1994-09-06 | Honeywell Inc. | SOI substrate fabrication |
| US5455193A (en) * | 1994-11-17 | 1995-10-03 | Philips Electronics North America Corporation | Method of forming a silicon-on-insulator (SOI) material having a high degree of thickness uniformity |
| WO1998042010A1 (en) * | 1997-03-17 | 1998-09-24 | Genus, Inc. | Bonded soi wafers using high energy implant |
| US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
| US5976941A (en) * | 1997-06-06 | 1999-11-02 | The Whitaker Corporation | Ultrahigh vacuum deposition of silicon (Si-Ge) on HMIC substrates |
| US6107653A (en) | 1997-06-24 | 2000-08-22 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
| US6040225A (en) * | 1997-08-29 | 2000-03-21 | The Whitaker Corporation | Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices |
| US6130471A (en) * | 1997-08-29 | 2000-10-10 | The Whitaker Corporation | Ballasting of high power silicon-germanium heterojunction biploar transistors |
| US6033995A (en) * | 1997-09-16 | 2000-03-07 | Trw Inc. | Inverted layer epitaxial liftoff process |
| FR2775121B1 (fr) * | 1998-02-13 | 2000-05-05 | Picogiga Sa | Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures |
| US7227176B2 (en) * | 1998-04-10 | 2007-06-05 | Massachusetts Institute Of Technology | Etch stop layer system |
| FR2789518B1 (fr) * | 1999-02-10 | 2003-06-20 | Commissariat Energie Atomique | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
| US6323108B1 (en) | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
| US6503773B2 (en) * | 2000-01-20 | 2003-01-07 | Amberwave Systems Corporation | Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
| US6750130B1 (en) | 2000-01-20 | 2004-06-15 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
| US6602613B1 (en) | 2000-01-20 | 2003-08-05 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
| US6392257B1 (en) * | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
| FR2805923B1 (fr) * | 2000-03-06 | 2002-05-24 | St Microelectronics Sa | Procede de fabrication d'un transistor bipolaire double- polysilicium auto-aligne |
| US6573126B2 (en) | 2000-08-16 | 2003-06-03 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
| US6890835B1 (en) | 2000-10-19 | 2005-05-10 | International Business Machines Corporation | Layer transfer of low defect SiGe using an etch-back process |
| US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| US20020100942A1 (en) * | 2000-12-04 | 2002-08-01 | Fitzgerald Eugene A. | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| EP1217656A1 (de) * | 2000-12-20 | 2002-06-26 | STMicroelectronics S.r.l. | Herstellungverfahren von Komponenten in einer Halbleiterscheibe mit Reduzierung der Anfangsdicke der Scheibe |
| US7026219B2 (en) * | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| KR101050377B1 (ko) * | 2001-02-12 | 2011-07-20 | 에이에스엠 아메리카, 인코포레이티드 | 반도체 박막 증착을 위한 개선된 공정 |
| US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6703688B1 (en) | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6723661B2 (en) * | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
| US20020158245A1 (en) * | 2001-04-26 | 2002-10-31 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing binary metal oxide layers |
| US20030012965A1 (en) * | 2001-07-10 | 2003-01-16 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate comprising an oxygen-doped compound semiconductor layer |
| US7019332B2 (en) * | 2001-07-20 | 2006-03-28 | Freescale Semiconductor, Inc. | Fabrication of a wavelength locker within a semiconductor structure |
| WO2003025984A2 (en) | 2001-09-21 | 2003-03-27 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
| WO2003028106A2 (en) * | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
| JP2003249641A (ja) * | 2002-02-22 | 2003-09-05 | Sharp Corp | 半導体基板、その製造方法及び半導体装置 |
| AU2003222003A1 (en) | 2002-03-14 | 2003-09-29 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
| WO2003091173A2 (en) * | 2002-04-23 | 2003-11-06 | Astropower, Inc. | Capping layer for crystallizing germanium, and substrate having thin crystallized germanium layer |
| US7307273B2 (en) | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
| US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
| US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
| US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
| US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
| US7615829B2 (en) | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
| US6946371B2 (en) | 2002-06-10 | 2005-09-20 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
| US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
| US7157119B2 (en) * | 2002-06-25 | 2007-01-02 | Ppg Industries Ohio, Inc. | Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US7049627B2 (en) | 2002-08-23 | 2006-05-23 | Amberwave Systems Corporation | Semiconductor heterostructures and related methods |
| US7594967B2 (en) | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
| US20040079285A1 (en) * | 2002-10-24 | 2004-04-29 | Motorola, Inc. | Automation of oxide material growth in molecular beam epitaxy systems |
| US6885065B2 (en) * | 2002-11-20 | 2005-04-26 | Freescale Semiconductor, Inc. | Ferromagnetic semiconductor structure and method for forming the same |
| US6963090B2 (en) * | 2003-01-09 | 2005-11-08 | Freescale Semiconductor, Inc. | Enhancement mode metal-oxide-semiconductor field effect transistor |
| JP4659732B2 (ja) | 2003-01-27 | 2011-03-30 | 台湾積體電路製造股▲ふん▼有限公司 | 半導体層を形成する方法 |
| CN100437970C (zh) | 2003-03-07 | 2008-11-26 | 琥珀波系统公司 | 一种结构及用于形成半导体结构的方法 |
| US7541614B2 (en) * | 2003-03-11 | 2009-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same |
| US20050054156A1 (en) * | 2003-09-10 | 2005-03-10 | International Business Machines Corporation | Capacitor and fabrication method using ultra-high vacuum cvd of silicon nitride |
| US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
| US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
| US8007675B1 (en) * | 2005-07-11 | 2011-08-30 | National Semiconductor Corporation | System and method for controlling an etch process for a single crystal having a buried layer |
| KR20080098632A (ko) * | 2006-01-31 | 2008-11-11 | 엠이엠씨 일렉트로닉 머티리얼즈, 인크. | 고 열 전도율을 가진 반도체 웨이퍼 |
| EP2532643A1 (de) | 2007-06-08 | 2012-12-12 | MannKind Corporation | IRE-1a-Inhibitoren |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3293087A (en) * | 1963-03-05 | 1966-12-20 | Fairchild Camera Instr Co | Method of making isolated epitaxial field-effect device |
| US3829889A (en) * | 1963-12-16 | 1974-08-13 | Signetics Corp | Semiconductor structure |
| US3455748A (en) * | 1965-05-24 | 1969-07-15 | Sprague Electric Co | Method of making a narrow base transistor |
| US4000020A (en) * | 1973-04-30 | 1976-12-28 | Texas Instruments Incorporated | Vapor epitaxial method for depositing gallium arsenide phosphide on germanium and silicon substrate wafers |
| US3969749A (en) * | 1974-04-01 | 1976-07-13 | Texas Instruments Incorporated | Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide |
| JPS5617083A (en) * | 1979-07-20 | 1981-02-18 | Hitachi Ltd | Semiconductor device and its manufacture |
| US4861393A (en) * | 1983-10-28 | 1989-08-29 | American Telephone And Telegraph Company, At&T Bell Laboratories | Semiconductor heterostructures having Gex Si1-x layers on Si utilizing molecular beam epitaxy |
| US4534804A (en) * | 1984-06-14 | 1985-08-13 | International Business Machines Corporation | Laser process for forming identically positioned alignment marks on the opposite sides of a semiconductor wafer |
| US4601779A (en) * | 1985-06-24 | 1986-07-22 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
| US4979015A (en) * | 1987-01-28 | 1990-12-18 | Texas Instruments Incorporated | Insulated substrate for flip-chip integrated circuit device |
| US4771016A (en) * | 1987-04-24 | 1988-09-13 | Harris Corporation | Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |
| JPH01290595A (ja) * | 1988-05-16 | 1989-11-22 | Touyoko Kagaku Kk | Ｓｉ／Ａｌ↓２Ｏ↓３／Ｓｉ多層構造の形成法 |
| US5147808A (en) * | 1988-11-02 | 1992-09-15 | Universal Energy Systems, Inc. | High energy ion implanted silicon on insulator structure |
| US4962051A (en) * | 1988-11-18 | 1990-10-09 | Motorola, Inc. | Method of forming a defect-free semiconductor layer on insulator |
| US5008207A (en) * | 1989-09-11 | 1991-04-16 | International Business Machines Corporation | Method of fabricating a narrow base transistor |
| US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
| US5261999A (en) * | 1991-05-08 | 1993-11-16 | North American Philips Corporation | Process for making strain-compensated bonded silicon-on-insulator material free of dislocations |
-
1992
- 1992-05-28 JP JP4161988A patent/JPH07187892A/ja active Pending
- 1992-06-03 EP EP92109320A patent/EP0520216B1/de not_active Expired - Lifetime
- 1992-06-03 DE DE69232749T patent/DE69232749T2/de not_active Expired - Lifetime
-
1994
- 1994-04-04 US US08/223,098 patent/US5540785A/en not_active Expired - Lifetime
- 1994-04-11 US US08/225,499 patent/US5462883A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07187892A (ja) | 1995-07-25 |
| US5540785A (en) | 1996-07-30 |
| EP0520216A3 (de) | 1995-06-07 |
| DE69232749D1 (de) | 2002-10-02 |
| EP0520216B1 (de) | 2002-08-28 |
| EP0520216A2 (de) | 1992-12-30 |
| US5462883A (en) | 1995-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8328 | Change in the person/name/address of the agent |
Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7 |