DE69303725D1 - Verbesserter schneller multiplizierer - Google Patents

Verbesserter schneller multiplizierer

Info

Publication number
DE69303725D1
DE69303725D1 DE69303725T DE69303725T DE69303725D1 DE 69303725 D1 DE69303725 D1 DE 69303725D1 DE 69303725 T DE69303725 T DE 69303725T DE 69303725 T DE69303725 T DE 69303725T DE 69303725 D1 DE69303725 D1 DE 69303725D1
Authority
DE
Germany
Prior art keywords
improved fast
fast multiplier
multiplier
improved
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69303725T
Other languages
English (en)
Inventor
Laurence Flora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/979,548 external-priority patent/US5343417A/en
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE69303725D1 publication Critical patent/DE69303725D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
DE69303725T 1992-11-20 1993-11-20 Verbesserter schneller multiplizierer Expired - Lifetime DE69303725D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/979,548 US5343417A (en) 1992-11-20 1992-11-20 Fast multiplier
US99456192A 1992-12-21 1992-12-21
PCT/US1993/011196 WO1994012928A1 (en) 1992-11-20 1993-11-20 Enhanced fast multiplier

Publications (1)

Publication Number Publication Date
DE69303725D1 true DE69303725D1 (de) 1996-08-22

Family

ID=27130606

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69303725T Expired - Lifetime DE69303725D1 (de) 1992-11-20 1993-11-20 Verbesserter schneller multiplizierer

Country Status (5)

Country Link
US (1) US5586071A (de)
EP (1) EP0670061B1 (de)
JP (1) JPH08504525A (de)
DE (1) DE69303725D1 (de)
WO (1) WO1994012928A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359965B1 (ko) * 1995-04-11 2003-03-15 캐논 가부시끼가이샤 프로세서와이의연산방법 및 데이타프로세서
US6065033A (en) * 1997-02-28 2000-05-16 Digital Equipment Corporation Wallace-tree multipliers using half and full adders
US5883825A (en) * 1997-09-03 1999-03-16 Lucent Technologies Inc. Reduction of partial product arrays using pre-propagate set-up
US6029187A (en) * 1997-10-28 2000-02-22 Atmel Corporation Fast regular multiplier architecture
US6037891A (en) * 1998-02-23 2000-03-14 Motorola, Inc. Low power serial analog-to-digital converter
US6122655A (en) * 1998-05-15 2000-09-19 Lucent Technologies Inc. Efficient use of inverting cells in multiplier converter
US6490608B1 (en) * 1999-12-09 2002-12-03 Synopsys, Inc. Fast parallel multiplier implemented with improved tree reduction schemes
GB0317570D0 (en) * 2003-07-26 2003-08-27 Koninkl Philips Electronics Nv Long-integer multiplier
US7451384B2 (en) * 2004-07-15 2008-11-11 Honeywell International Inc. Error recovery in asynchronous combinational logic circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146421A (en) * 1987-11-24 1992-09-08 Digital Equipment Corporation High speed parallel multiplier circuit
JPH0776914B2 (ja) * 1988-10-18 1995-08-16 三菱電機株式会社 乗算回路
US5101372A (en) * 1990-09-28 1992-03-31 International Business Machines Corporation Optimum performance standard cell array multiplier
US5072419A (en) * 1990-11-21 1991-12-10 Sun Microsystems, Inc. Binary tree multiplier constructed of carry save adders having an area efficient floor plan

Also Published As

Publication number Publication date
US5586071A (en) 1996-12-17
WO1994012928A1 (en) 1994-06-09
EP0670061B1 (de) 1996-07-17
JPH08504525A (ja) 1996-05-14
EP0670061A1 (de) 1995-09-06

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Legal Events

Date Code Title Description
8332 No legal effect for de