DE69305366T2 - System und verfahren zum kennzeichnen von befehlen zur steuerung der befehlsausführung - Google Patents

System und verfahren zum kennzeichnen von befehlen zur steuerung der befehlsausführung

Info

Publication number
DE69305366T2
DE69305366T2 DE69305366T DE69305366T DE69305366T2 DE 69305366 T2 DE69305366 T2 DE 69305366T2 DE 69305366 T DE69305366 T DE 69305366T DE 69305366 T DE69305366 T DE 69305366T DE 69305366 T2 DE69305366 T2 DE 69305366T2
Authority
DE
Germany
Prior art keywords
controlling
command execution
labeling
commands
labeling commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69305366T
Other languages
English (en)
Other versions
DE69305366D1 (de
Inventor
Kevin Iadonato
Trevor Deosaran
Sanjiv Garg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of DE69305366D1 publication Critical patent/DE69305366D1/de
Publication of DE69305366T2 publication Critical patent/DE69305366T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
DE69305366T 1992-12-31 1993-12-16 System und verfahren zum kennzeichnen von befehlen zur steuerung der befehlsausführung Expired - Lifetime DE69305366T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/999,648 US5604912A (en) 1992-12-31 1992-12-31 System and method for assigning tags to instructions to control instruction execution
PCT/US1993/012309 WO1994016385A1 (en) 1992-12-31 1993-12-16 System and method for assigning tags to instructions to control instruction execution

Publications (2)

Publication Number Publication Date
DE69305366D1 DE69305366D1 (de) 1996-11-14
DE69305366T2 true DE69305366T2 (de) 1997-02-20

Family

ID=25546575

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69305366T Expired - Lifetime DE69305366T2 (de) 1992-12-31 1993-12-16 System und verfahren zum kennzeichnen von befehlen zur steuerung der befehlsausführung

Country Status (6)

Country Link
US (2) US5604912A (de)
EP (1) EP0677188B1 (de)
JP (1) JP3531167B2 (de)
KR (1) KR100295081B1 (de)
DE (1) DE69305366T2 (de)
WO (1) WO1994016385A1 (de)

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US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JP3730252B2 (ja) * 1992-03-31 2005-12-21 トランスメタ コーポレイション レジスタ名称変更方法及び名称変更システム
WO1993022722A1 (en) * 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
EP1107111A3 (de) * 1992-12-31 2002-02-06 Seiko Epson Corporation System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US6035424A (en) * 1996-12-09 2000-03-07 International Business Machines Corporation Method and apparatus for tracking processing of a command
US5948098A (en) * 1997-06-30 1999-09-07 Sun Microsystems, Inc. Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines
US6237083B1 (en) 1998-02-13 2001-05-22 Advanced Micro Devices, Inc. Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence
US6859874B2 (en) * 2001-09-24 2005-02-22 Broadcom Corporation Method for identifying basic blocks with conditional delay slot instructions
US6883090B2 (en) * 2001-05-17 2005-04-19 Broadcom Corporation Method for cancelling conditional delay slot instructions
US6785804B2 (en) * 2001-05-17 2004-08-31 Broadcom Corporation Use of tags to cancel a conditional branch delay slot instruction
US20030041073A1 (en) * 2001-08-21 2003-02-27 Collier Josh D. Method and apparatus for reordering received messages for improved processing performance
US6813704B1 (en) * 2001-12-20 2004-11-02 Lsi Logic Corporation Changing instruction order by reassigning only tags in order tag field in instruction queue
US7398375B2 (en) * 2002-04-04 2008-07-08 The Regents Of The University Of Michigan Technique for reduced-tag dynamic scheduling and reduced-tag prediction
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US10229066B2 (en) * 2016-09-30 2019-03-12 Arm Limited Queuing memory access requests
US11709681B2 (en) 2017-12-11 2023-07-25 Advanced Micro Devices, Inc. Differential pipeline delays in a coprocessor
US11567554B2 (en) * 2017-12-11 2023-01-31 Advanced Micro Devices, Inc. Clock mesh-based power conservation in a coprocessor based on in-flight instruction characteristics
US11263013B2 (en) * 2020-04-07 2022-03-01 Andes Technology Corporation Processor having read shifter and controlling method using the same
CN111966406B (zh) * 2020-08-06 2021-03-23 北京微核芯科技有限公司 乱序处理器中乱序执行队列的调度方法和装置

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US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
JPH0762823B2 (ja) * 1985-05-22 1995-07-05 株式会社日立製作所 デ−タ処理装置
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JP2684362B2 (ja) * 1986-06-18 1997-12-03 株式会社日立製作所 可変長データの記憶方式
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US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
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US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5109495A (en) * 1989-02-03 1992-04-28 Digital Equipment Corp. Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor
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US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5251306A (en) * 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
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US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
DE69127936T2 (de) * 1990-06-29 1998-05-07 Digital Equipment Corp Busprotokoll für Prozessor mit write-back cache
US5655096A (en) * 1990-10-12 1997-08-05 Branigin; Michael H. Method and apparatus for dynamic scheduling of instructions to ensure sequentially coherent data in a processor employing out-of-order execution
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US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
JPH0621466Y2 (ja) * 1991-11-11 1994-06-08 キャピーインターナショナル株式会社 担 架
US5285527A (en) * 1991-12-11 1994-02-08 Northern Telecom Limited Predictive historical cache memory
US5398330A (en) * 1992-03-05 1995-03-14 Seiko Epson Corporation Register file backup queue
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5604912A (en) * 1992-12-31 1997-02-18 Seiko Epson Corporation System and method for assigning tags to instructions to control instruction execution

Also Published As

Publication number Publication date
EP0677188B1 (de) 1996-10-09
WO1994016385A1 (en) 1994-07-21
KR960700475A (ko) 1996-01-20
JPH08505725A (ja) 1996-06-18
KR100295081B1 (ko) 2001-09-17
EP0677188A1 (de) 1995-10-18
US5604912A (en) 1997-02-18
JP3531167B2 (ja) 2004-05-24
DE69305366D1 (de) 1996-11-14
US5892963A (en) 1999-04-06

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