DE69312196T2 - Verfahren zur Vorbereitung der Montage eines Chips auf einem Substrat - Google Patents

Verfahren zur Vorbereitung der Montage eines Chips auf einem Substrat

Info

Publication number
DE69312196T2
DE69312196T2 DE1993612196 DE69312196T DE69312196T2 DE 69312196 T2 DE69312196 T2 DE 69312196T2 DE 1993612196 DE1993612196 DE 1993612196 DE 69312196 T DE69312196 T DE 69312196T DE 69312196 T2 DE69312196 T2 DE 69312196T2
Authority
DE
Germany
Prior art keywords
chip
preparing
substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1993612196
Other languages
English (en)
Other versions
DE69312196D1 (de
Inventor
Alain Grancher
Ludovic Michel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of DE69312196D1 publication Critical patent/DE69312196D1/de
Application granted granted Critical
Publication of DE69312196T2 publication Critical patent/DE69312196T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/45015—Cross-sectional shape being circular
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/484—Connecting portions
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    • H01L2224/85009—Pre-treatment of the connector or the bonding area
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    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
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    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
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    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
DE1993612196 1992-09-25 1993-09-10 Verfahren zur Vorbereitung der Montage eines Chips auf einem Substrat Expired - Fee Related DE69312196T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9211447A FR2696279B1 (fr) 1992-09-25 1992-09-25 Procédé pour permettre le montage d'une puce sur un substrat et puce préparée selon le procédé.

Publications (2)

Publication Number Publication Date
DE69312196D1 DE69312196D1 (de) 1997-08-21
DE69312196T2 true DE69312196T2 (de) 1997-10-30

Family

ID=9433889

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1993612196 Expired - Fee Related DE69312196T2 (de) 1992-09-25 1993-09-10 Verfahren zur Vorbereitung der Montage eines Chips auf einem Substrat

Country Status (4)

Country Link
US (1) US5438020A (de)
EP (1) EP0589748B1 (de)
DE (1) DE69312196T2 (de)
FR (1) FR2696279B1 (de)

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JP3304720B2 (ja) * 1995-10-31 2002-07-22 日立電線株式会社 リードフレームへの接着剤塗布方法
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
TW337033B (en) * 1996-02-08 1998-07-21 Matsushita Electric Ind Co Ltd Bump forming method and its forming apparatus
US5771157A (en) * 1996-03-08 1998-06-23 Honeywell, Inc. Chip-on-board printed circuit assembly using aluminum wire bonded to copper pads
US6179198B1 (en) * 1996-09-18 2001-01-30 Matsushita Electric Industrial Co., Ltd. Method of soldering bumped work by partially penetrating the oxide film covering the solder bumps
JP3425510B2 (ja) * 1996-09-27 2003-07-14 松下電器産業株式会社 バンプボンダー形成方法
US6293456B1 (en) 1997-05-27 2001-09-25 Spheretek, Llc Methods for forming solder balls on substrates
US7007833B2 (en) 1997-05-27 2006-03-07 Mackay John Forming solder balls on substrates
US7842599B2 (en) * 1997-05-27 2010-11-30 Wstp, Llc Bumping electronic components using transfer substrates
US6609652B2 (en) 1997-05-27 2003-08-26 Spheretek, Llc Ball bumping substrates, particuarly wafers
US7819301B2 (en) * 1997-05-27 2010-10-26 Wstp, Llc Bumping electronic components using transfer substrates
US7288471B2 (en) * 1997-05-27 2007-10-30 Mackay John Bumping electronic components using transfer substrates
US7654432B2 (en) 1997-05-27 2010-02-02 Wstp, Llc Forming solder balls on substrates
US5988487A (en) * 1997-05-27 1999-11-23 Fujitsu Limited Captured-cell solder printing and reflow methods
FR2769130B1 (fr) 1997-09-30 2001-06-08 Thomson Csf Procede d'enrobage d'une puce electronique et carte electronique comportant au moins une puce enrobee selon ce procede
US6765652B1 (en) * 1998-01-12 2004-07-20 Micron Technology, Inc. Forming thermally curable materials on a support structure in an electronic device
KR20120091839A (ko) * 2011-02-10 2012-08-20 삼성전자주식회사 플립칩 발광소자 패키지 및 그 제조 방법

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US3621565A (en) * 1969-06-12 1971-11-23 Nasa Fabrication of single-crystal film semiconductor devices
JPS6482643A (en) * 1987-09-25 1989-03-28 Fujitsu Ltd Manufacture of resin sealed semiconductor device
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FR2696279B1 (fr) 1994-11-18
DE69312196D1 (de) 1997-08-21
US5438020A (en) 1995-08-01
EP0589748A1 (de) 1994-03-30
EP0589748B1 (de) 1997-07-16
FR2696279A1 (fr) 1994-04-01

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