DE69312786T2 - Externes Interface für einen hochleistungsfähigen Graphikadapter, das die graphische Kompatibilität gewährt - Google Patents
Externes Interface für einen hochleistungsfähigen Graphikadapter, das die graphische Kompatibilität gewährtInfo
- Publication number
- DE69312786T2 DE69312786T2 DE69312786T DE69312786T DE69312786T2 DE 69312786 T2 DE69312786 T2 DE 69312786T2 DE 69312786 T DE69312786 T DE 69312786T DE 69312786 T DE69312786 T DE 69312786T DE 69312786 T2 DE69312786 T2 DE 69312786T2
- Authority
- DE
- Germany
- Prior art keywords
- graphic
- guarantees
- compatibility
- external interface
- graphics adapter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/206—Memory mapped I/O
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
- G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/08—Cursor circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US87656992A | 1992-04-30 | 1992-04-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69312786D1 DE69312786D1 (de) | 1997-09-11 |
DE69312786T2 true DE69312786T2 (de) | 1998-03-05 |
Family
ID=25368038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69312786T Expired - Fee Related DE69312786T2 (de) | 1992-04-30 | 1993-04-29 | Externes Interface für einen hochleistungsfähigen Graphikadapter, das die graphische Kompatibilität gewährt |
Country Status (4)
Country | Link |
---|---|
US (2) | US5438663A (de) |
EP (1) | EP0568078B1 (de) |
JP (1) | JP2760731B2 (de) |
DE (1) | DE69312786T2 (de) |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2760731B2 (ja) * | 1992-04-30 | 1998-06-04 | 株式会社東芝 | グラフィックス互換性を可能にする高性能グラフィックスアダプタ用外部インターフェース回路 |
US8821276B2 (en) | 1992-05-22 | 2014-09-02 | Bassilic Technologies Llc | Image integration, mapping and linking system and methodology |
US5553864A (en) | 1992-05-22 | 1996-09-10 | Sitrick; David H. | User image integration into audiovisual presentation system and methodology |
CA2097564C (en) * | 1992-06-16 | 2004-05-25 | David L. Phillips | Method of coupling open systems to a proprietary network |
US5675750A (en) * | 1993-11-12 | 1997-10-07 | Toshiba America Information Systems | Interface having a bus master arbitrator for arbitrating occupation and release of a common bus between a host processor and a graphics system processor |
EP0663659A3 (de) * | 1993-12-30 | 1995-11-22 | Ibm | Anzeige von Zeichen in einem Datenverarbeitungssystem. |
US5477242A (en) * | 1994-01-03 | 1995-12-19 | International Business Machines Corporation | Display adapter for virtual VGA support in XGA native mode |
US5664162A (en) * | 1994-05-23 | 1997-09-02 | Cirrus Logic, Inc. | Graphics accelerator with dual memory controllers |
US5646651A (en) * | 1994-12-14 | 1997-07-08 | Spannaus; John | Block mode, multiple access multi-media/graphics memory |
US5687376A (en) * | 1994-12-15 | 1997-11-11 | International Business Machines Corporation | System for monitoring performance of advanced graphics driver including filter modules for passing supported commands associated with function calls and recording task execution time for graphic operation |
US5862343A (en) * | 1995-02-10 | 1999-01-19 | National Semiconductor Corporation | Circuit for logical stream sorting at CPU transfer time division for multiplexed (TDM) including bus interface circuitry |
US5784076A (en) * | 1995-06-07 | 1998-07-21 | International Business Machines Corporation | Video processor implementing various data translations using control registers |
US5838934A (en) * | 1995-06-07 | 1998-11-17 | Texas Instruments Incorporated | Host port interface |
US5835134A (en) * | 1995-10-13 | 1998-11-10 | Digital Equipment Corporation | Calibration and merging unit for video adapters |
JPH09114443A (ja) | 1995-10-20 | 1997-05-02 | Seiko Epson Corp | 映像スケーリング装置 |
JP3491471B2 (ja) * | 1995-11-06 | 2004-01-26 | セイコーエプソン株式会社 | 駆動装置及び電子機器 |
US5781201A (en) * | 1996-05-01 | 1998-07-14 | Digital Equipment Corporation | Method for providing improved graphics performance through atypical pixel storage in video memory |
US5812393A (en) * | 1996-05-14 | 1998-09-22 | Microwave Science, Llc | Interpretive BIOS machine and method of use thereof |
US5883801A (en) * | 1996-05-14 | 1999-03-16 | Microwave Science, Llc | Method and apparatus for managing electromagnetic radiation usage |
US5903261A (en) * | 1996-06-20 | 1999-05-11 | Data Translation, Inc. | Computer based video system |
US6266753B1 (en) | 1997-07-10 | 2001-07-24 | Cirrus Logic, Inc. | Memory manager for multi-media apparatus and method therefor |
US6167498A (en) * | 1997-10-02 | 2000-12-26 | Cirrus Logic, Inc. | Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats |
US6542938B1 (en) | 1997-12-23 | 2003-04-01 | Seiko Epson Corporation | Mechanism and apparatus for adaptive quality performance control in 3D based PC applications |
US6212593B1 (en) * | 1998-06-01 | 2001-04-03 | Advanced Micro Devices, Inc. | Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system |
US6215507B1 (en) * | 1998-06-01 | 2001-04-10 | Texas Instruments Incorporated | Display system with interleaved pixel address |
US6618048B1 (en) | 1999-10-28 | 2003-09-09 | Nintendo Co., Ltd. | 3D graphics rendering system for performing Z value clamping in near-Z range to maximize scene resolution of visually important Z components |
US6411301B1 (en) | 1999-10-28 | 2002-06-25 | Nintendo Co., Ltd. | Graphics system interface |
US6717577B1 (en) | 1999-10-28 | 2004-04-06 | Nintendo Co., Ltd. | Vertex cache for 3D computer graphics |
US6452600B1 (en) | 1999-10-28 | 2002-09-17 | Nintendo Co., Ltd. | Graphics system interface |
US7119813B1 (en) | 2000-06-02 | 2006-10-10 | Nintendo Co., Ltd. | Variable bit field encoding |
US6811489B1 (en) | 2000-08-23 | 2004-11-02 | Nintendo Co., Ltd. | Controller interface for a graphics system |
US6707458B1 (en) | 2000-08-23 | 2004-03-16 | Nintendo Co., Ltd. | Method and apparatus for texture tiling in a graphics system |
US7061502B1 (en) | 2000-08-23 | 2006-06-13 | Nintendo Co., Ltd. | Method and apparatus for providing logical combination of N alpha operations within a graphics system |
US6980218B1 (en) | 2000-08-23 | 2005-12-27 | Nintendo Co., Ltd. | Method and apparatus for efficient generation of texture coordinate displacements for implementing emboss-style bump mapping in a graphics rendering system |
US7576748B2 (en) | 2000-11-28 | 2009-08-18 | Nintendo Co. Ltd. | Graphics system with embedded frame butter having reconfigurable pixel formats |
US7184059B1 (en) | 2000-08-23 | 2007-02-27 | Nintendo Co., Ltd. | Graphics system with copy out conversions between embedded frame buffer and main memory |
US6825851B1 (en) | 2000-08-23 | 2004-11-30 | Nintendo Co., Ltd. | Method and apparatus for environment-mapped bump-mapping in a graphics system |
US6867781B1 (en) | 2000-08-23 | 2005-03-15 | Nintendo Co., Ltd. | Graphics pipeline token synchronization |
US7196710B1 (en) | 2000-08-23 | 2007-03-27 | Nintendo Co., Ltd. | Method and apparatus for buffering graphics data in a graphics system |
US6700586B1 (en) | 2000-08-23 | 2004-03-02 | Nintendo Co., Ltd. | Low cost graphics with stitching processing hardware support for skeletal animation |
US6636214B1 (en) | 2000-08-23 | 2003-10-21 | Nintendo Co., Ltd. | Method and apparatus for dynamically reconfiguring the order of hidden surface processing based on rendering mode |
US6937245B1 (en) | 2000-08-23 | 2005-08-30 | Nintendo Co., Ltd. | Graphics system with embedded frame buffer having reconfigurable pixel formats |
US7034828B1 (en) | 2000-08-23 | 2006-04-25 | Nintendo Co., Ltd. | Recirculating shade tree blender for a graphics system |
US7002591B1 (en) | 2000-08-23 | 2006-02-21 | Nintendo Co., Ltd. | Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system |
US7538772B1 (en) | 2000-08-23 | 2009-05-26 | Nintendo Co., Ltd. | Graphics processing system with enhanced memory controller |
US6697074B2 (en) | 2000-11-28 | 2004-02-24 | Nintendo Co., Ltd. | Graphics system interface |
US6925514B1 (en) * | 2001-03-30 | 2005-08-02 | Agere Systems Inc. | Multi-protocol bus system and method of operation thereof |
CN1295595C (zh) * | 2001-12-13 | 2007-01-17 | 微软公司 | 通用图形适配器以及调度i/o服务请求的方法 |
US6907482B2 (en) * | 2001-12-13 | 2005-06-14 | Microsoft Corporation | Universal graphic adapter for interfacing with hardware and means for encapsulating and abstracting details of the hardware |
TWI340960B (en) * | 2002-04-19 | 2011-04-21 | Tpo Hong Kong Holding Ltd | Programmable drivers for display device |
US7336268B1 (en) * | 2002-10-30 | 2008-02-26 | National Semiconductor Corporation | Point-to-point display system having configurable connections |
GB0301448D0 (en) * | 2003-01-22 | 2003-02-19 | Falanx Microsystems As | Microprocessor systems |
US7106339B1 (en) * | 2003-04-09 | 2006-09-12 | Intel Corporation | System with local unified memory architecture and method |
US7498559B2 (en) | 2004-09-22 | 2009-03-03 | Sharp Kabushiki Kaisha | Optical discharge apparatus and image forming apparatus containing the same |
US7721118B1 (en) | 2004-09-27 | 2010-05-18 | Nvidia Corporation | Optimizing power and performance for multi-processor graphics processing |
EP1657936A1 (de) * | 2004-11-10 | 2006-05-17 | Sony Ericsson Mobile Communications AB | Weissabgleichseinstellungsvorrichtung |
US7576745B1 (en) | 2004-11-17 | 2009-08-18 | Nvidia Corporation | Connecting graphics adapters |
US8066515B2 (en) * | 2004-11-17 | 2011-11-29 | Nvidia Corporation | Multiple graphics adapter connection systems |
US7697011B2 (en) * | 2004-12-10 | 2010-04-13 | Honeywell International Inc. | Automatic display video positioning and scaling system |
US8134568B1 (en) | 2004-12-15 | 2012-03-13 | Nvidia Corporation | Frame buffer region redirection for multiple graphics adapters |
US8212831B1 (en) | 2004-12-15 | 2012-07-03 | Nvidia Corporation | Broadcast aperture remapping for multiple graphics adapters |
US7308565B2 (en) * | 2005-06-15 | 2007-12-11 | Seiko Epson Corporation | Saving/restoring task state data from/to device controller host interface upon command from host processor to handle task interruptions |
JP2007078937A (ja) | 2005-09-13 | 2007-03-29 | Canon Inc | 画像形成装置 |
US20070101325A1 (en) * | 2005-10-19 | 2007-05-03 | Juraj Bystricky | System and method for utilizing a remote memory to perform an interface save/restore procedure |
US7545382B1 (en) * | 2006-03-29 | 2009-06-09 | Nvidia Corporation | Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation |
US7698579B2 (en) * | 2006-08-03 | 2010-04-13 | Apple Inc. | Multiplexed graphics architecture for graphics power management |
US9081706B2 (en) * | 2012-05-10 | 2015-07-14 | Oracle International Corporation | Using a shared last-level TLB to reduce address-translation latency |
US9009446B2 (en) * | 2012-08-02 | 2015-04-14 | Oracle International Corporation | Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect |
US10387343B2 (en) | 2015-04-07 | 2019-08-20 | International Business Machines Corporation | Processing of events for accelerators utilized for parallel processing |
JP2017219586A (ja) * | 2016-06-03 | 2017-12-14 | 株式会社ジャパンディスプレイ | 信号供給回路及び表示装置 |
CN111273883A (zh) * | 2020-01-20 | 2020-06-12 | 北京远特科技股份有限公司 | 多操作系统的同屏显示方法、装置和终端设备 |
US11429451B2 (en) | 2020-01-22 | 2022-08-30 | Microsoft Technology Licensing, Llc | Managing exceptions on a shared resource |
CN114327627B (zh) * | 2021-12-15 | 2023-01-03 | 中国船舶重工集团公司第七0九研究所 | 一种实模式下基于gpu传统io配置显示分辨率的方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4992961A (en) * | 1988-12-01 | 1991-02-12 | Hewlett-Packard Company | Method and apparatus for increasing image generation speed on raster displays |
US4958378A (en) * | 1989-04-26 | 1990-09-18 | Sun Microsystems, Inc. | Method and apparatus for detecting changes in raster data |
JPH03246596A (ja) * | 1990-02-26 | 1991-11-01 | Matsushita Electric Ind Co Ltd | ビットマップディスプレイ制御装置 |
US5119494A (en) * | 1990-07-10 | 1992-06-02 | Athenix Corporation | Application address display window mapper for a sharable ms-dos processor |
JP2760731B2 (ja) * | 1992-04-30 | 1998-06-04 | 株式会社東芝 | グラフィックス互換性を可能にする高性能グラフィックスアダプタ用外部インターフェース回路 |
-
1993
- 1993-04-28 JP JP5123281A patent/JP2760731B2/ja not_active Expired - Lifetime
- 1993-04-29 EP EP93106998A patent/EP0568078B1/de not_active Expired - Lifetime
- 1993-04-29 DE DE69312786T patent/DE69312786T2/de not_active Expired - Fee Related
- 1993-11-12 US US08/150,779 patent/US5438663A/en not_active Expired - Fee Related
-
1995
- 1995-04-06 US US08/419,065 patent/US5522027A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0568078A1 (de) | 1993-11-03 |
EP0568078B1 (de) | 1997-08-06 |
JP2760731B2 (ja) | 1998-06-04 |
DE69312786D1 (de) | 1997-09-11 |
US5522027A (en) | 1996-05-28 |
JPH0659856A (ja) | 1994-03-04 |
US5438663A (en) | 1995-08-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |