DE69322248D1 - Reservierung, die den normalen vorrang von mikroprozessoren in multiprozessorrechnersystemen annulliert - Google Patents

Reservierung, die den normalen vorrang von mikroprozessoren in multiprozessorrechnersystemen annulliert

Info

Publication number
DE69322248D1
DE69322248D1 DE69322248T DE69322248T DE69322248D1 DE 69322248 D1 DE69322248 D1 DE 69322248D1 DE 69322248 T DE69322248 T DE 69322248T DE 69322248 T DE69322248 T DE 69322248T DE 69322248 D1 DE69322248 D1 DE 69322248D1
Authority
DE
Germany
Prior art keywords
bus
priority
bus master
host bus
host
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69322248T
Other languages
English (en)
Other versions
DE69322248T2 (de
Inventor
Maria Melo
Jeff Wolford
Michael Moriarty
Paul Culley
Arnold Schnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of DE69322248D1 publication Critical patent/DE69322248D1/de
Application granted granted Critical
Publication of DE69322248T2 publication Critical patent/DE69322248T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
DE69322248T 1992-10-02 1993-09-29 Reservierung, die den normalen vorrang von mikroprozessoren in multiprozessorrechnersystemen annulliert Expired - Lifetime DE69322248T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/956,034 US5553248A (en) 1992-10-02 1992-10-02 System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
PCT/US1993/009362 WO1994008302A1 (en) 1992-10-02 1993-09-29 Reservation overriding normal prioritization of microprocessors in multiprocessing computer systems

Publications (2)

Publication Number Publication Date
DE69322248D1 true DE69322248D1 (de) 1999-01-07
DE69322248T2 DE69322248T2 (de) 1999-04-22

Family

ID=25497682

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322248T Expired - Lifetime DE69322248T2 (de) 1992-10-02 1993-09-29 Reservierung, die den normalen vorrang von mikroprozessoren in multiprozessorrechnersystemen annulliert

Country Status (8)

Country Link
US (1) US5553248A (de)
EP (1) EP0615640B1 (de)
JP (1) JP2742728B2 (de)
AT (1) ATE173842T1 (de)
AU (1) AU5168993A (de)
CA (1) CA2121720A1 (de)
DE (1) DE69322248T2 (de)
WO (1) WO1994008302A1 (de)

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JP4030216B2 (ja) * 1999-03-09 2008-01-09 インターナショナル・ビジネス・マシーンズ・コーポレーション マイクロプロセッサとマイクロプロセッサを含むシステム及びマイクロプロセッサのバスサイクル制御方法
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US6772254B2 (en) 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
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US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US6976132B2 (en) * 2003-03-28 2005-12-13 International Business Machines Corporation Reducing latency of a snoop tenure
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Also Published As

Publication number Publication date
CA2121720A1 (en) 1994-04-14
JP2742728B2 (ja) 1998-04-22
EP0615640B1 (de) 1998-11-25
DE69322248T2 (de) 1999-04-22
AU5168993A (en) 1994-04-26
ATE173842T1 (de) 1998-12-15
EP0615640A1 (de) 1994-09-21
US5553248A (en) 1996-09-03
WO1994008302A1 (en) 1994-04-14
JPH06511101A (ja) 1994-12-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition