DE69330240D1 - Dynamischer Speicher mit wahlfreiem Zugriff mit Parallelprüfmodus zur Erzeugung beliebiger Testmuster - Google Patents

Dynamischer Speicher mit wahlfreiem Zugriff mit Parallelprüfmodus zur Erzeugung beliebiger Testmuster

Info

Publication number
DE69330240D1
DE69330240D1 DE69330240T DE69330240T DE69330240D1 DE 69330240 D1 DE69330240 D1 DE 69330240D1 DE 69330240 T DE69330240 T DE 69330240T DE 69330240 T DE69330240 T DE 69330240T DE 69330240 D1 DE69330240 D1 DE 69330240D1
Authority
DE
Germany
Prior art keywords
test
random access
data storage
bit
generate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69330240T
Other languages
English (en)
Inventor
Toshio Takeshima
Tadahiko Sugibayashi
Isao Naritake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69330240D1 publication Critical patent/DE69330240D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
DE69330240T 1992-09-25 1993-09-27 Dynamischer Speicher mit wahlfreiem Zugriff mit Parallelprüfmodus zur Erzeugung beliebiger Testmuster Expired - Lifetime DE69330240D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4256650A JPH06203597A (ja) 1992-09-25 1992-09-25 ダイナミックｒａｍ

Publications (1)

Publication Number Publication Date
DE69330240D1 true DE69330240D1 (de) 2001-06-28

Family

ID=17295563

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330240T Expired - Lifetime DE69330240D1 (de) 1992-09-25 1993-09-27 Dynamischer Speicher mit wahlfreiem Zugriff mit Parallelprüfmodus zur Erzeugung beliebiger Testmuster

Country Status (5)

Country Link
US (1) US5436910A (de)
EP (1) EP0591811B1 (de)
JP (1) JPH06203597A (de)
KR (1) KR960001305B1 (de)
DE (1) DE69330240D1 (de)

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JPH06295599A (ja) * 1993-04-09 1994-10-21 Nec Corp 半導体記憶装置
JPH07334985A (ja) * 1994-06-08 1995-12-22 Mitsubishi Electric Corp 半導体記憶装置
US6438718B1 (en) * 1994-06-15 2002-08-20 Texas Instruments Incorporated Wordline stress mode arrangement a storage cell initialization scheme test time reduction burn-in elimination
DE69525035T2 (de) * 1994-11-09 2002-09-05 Koninkl Philips Electronics Nv Verfahren zum testen einer speicheradressen-dekodierschaltung
JP3666671B2 (ja) * 1994-12-20 2005-06-29 株式会社日立製作所 半導体装置
US5574692A (en) * 1995-06-07 1996-11-12 Lsi Logic Corporation Memory testing apparatus for microelectronic integrated circuit
US5796246A (en) * 1996-05-29 1998-08-18 Texas Instruments Incorporated Test board and process of testing wide word memory parts
US5787097A (en) * 1996-07-22 1998-07-28 Micron Technology, Inc. Output data compression scheme for use in testing IC memories
KR100206710B1 (ko) * 1996-09-23 1999-07-01 윤종용 반도체 메모리 장치의 웨이퍼 번인 테스트 회로
US5826006A (en) * 1996-09-30 1998-10-20 International Business Machines Corporation Method and apparatus for testing the data output system of a memory system
US5802070A (en) * 1996-10-03 1998-09-01 International Business Machines Corporation Testing associative memory
US6519725B1 (en) 1997-03-04 2003-02-11 International Business Machines Corporation Diagnosis of RAMS using functional patterns
KR100257580B1 (ko) * 1997-11-25 2000-06-01 윤종용 반도체 메모리 장치의 번-인 제어 회로
KR100487634B1 (ko) * 1997-12-30 2005-08-04 주식회사 하이닉스반도체 반도체메모리소자의블록콘트롤회로
JP4540137B2 (ja) * 1998-07-24 2010-09-08 ルネサスエレクトロニクス株式会社 同期型半導体記憶装置
US6317852B1 (en) * 1998-10-23 2001-11-13 Vanguard International Semiconductor Corporation Method to test auto-refresh and self refresh circuitry
JP3177966B2 (ja) * 1998-11-12 2001-06-18 日本電気株式会社 半導体記憶装置
US6421810B1 (en) * 1999-05-05 2002-07-16 National Semiconductor Corporation Scalable parallel test bus and testing method
KR100301822B1 (ko) * 1999-07-21 2001-11-01 김영환 불휘발성 강유전체 메모리 장치의 센싱앰프
TW444127B (en) * 1999-08-20 2001-07-01 Taiwan Semiconductor Mfg Comparing circuit, testing circuit and testing method for the parallel test of DRAM devices
US6768654B2 (en) * 2000-09-18 2004-07-27 Wavezero, Inc. Multi-layered structures and methods for manufacturing the multi-layered structures
DE10133689C2 (de) * 2001-07-11 2003-12-18 Infineon Technologies Ag Testverfahren und Testvorrichtung für elektronische Speicher
US6640296B2 (en) * 2002-03-07 2003-10-28 Nokia Corporation Data processing method and device for parallel stride access
JP3970716B2 (ja) * 2002-08-05 2007-09-05 松下電器産業株式会社 半導体記憶装置およびその検査方法
US7103814B2 (en) * 2002-10-25 2006-09-05 International Business Machines Corporation Testing logic and embedded memory in parallel
US6925588B2 (en) * 2002-12-23 2005-08-02 Lsi Logic Corporation Methods and apparatus for testing data lines
JP2006120250A (ja) 2004-10-21 2006-05-11 Fujitsu Ltd 半導体装置およびその試験方法
KR100809070B1 (ko) * 2006-06-08 2008-03-03 삼성전자주식회사 반도체 메모리 장치의 병렬 비트 테스트 회로 및 그 방법
JP5527957B2 (ja) * 2008-01-30 2014-06-25 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置及びその制御方法
TWI426519B (zh) * 2009-12-29 2014-02-11 Winbond Electronics Corp 記憶體晶片以及其控制方法
JP2012014769A (ja) * 2010-06-30 2012-01-19 Elpida Memory Inc 半導体装置およびそのテスト方法
CN103543980B (zh) * 2013-11-07 2021-10-22 吴胜远 数字数据处理的方法及装置
DE102020113510A1 (de) * 2020-05-19 2021-11-25 Tmd Friction Services Gmbh Dämpfungsmaterial für eine Dämpfungs- oder Zwischenschicht für Bremsbeläge und ein Verfahren zur Herstellung des Dämpfungsmaterials

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61261895A (ja) * 1985-05-16 1986-11-19 Toshiba Corp 半導体記憶装置
JPS6337894A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp ランダムアクセスメモリ
EP0264893B1 (de) * 1986-10-20 1995-01-18 Nippon Telegraph And Telephone Corporation Halbleiterspeicher
JP2582587B2 (ja) * 1987-09-18 1997-02-19 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
JPH0793040B2 (ja) * 1987-11-11 1995-10-09 日本電気株式会社 書込み・消去可能な読出し専用メモリ
JPH02177200A (ja) * 1988-12-28 1990-07-10 Sharp Corp 半導体記憶装置のテスト装置
US5222038A (en) * 1989-06-13 1993-06-22 Kabushiki Kaisha Toshiba Dynamic random access memory with enhanced sense-amplifier circuit
JP2717712B2 (ja) * 1989-08-18 1998-02-25 三菱電機株式会社 半導体記憶装置
JPH03162800A (ja) * 1989-08-29 1991-07-12 Mitsubishi Electric Corp 半導体メモリ装置
JPH0387000A (ja) * 1989-08-30 1991-04-11 Mitsubishi Electric Corp 半導体記憶装置
JP3100617B2 (ja) * 1990-10-23 2000-10-16 沖電気工業株式会社 半導体装置
JP3084759B2 (ja) * 1991-01-29 2000-09-04 日本電気株式会社 ダイナミックランダムアクセスメモリ装置

Also Published As

Publication number Publication date
EP0591811A2 (de) 1994-04-13
US5436910A (en) 1995-07-25
KR960001305B1 (ko) 1996-01-25
KR940007894A (ko) 1994-04-28
EP0591811B1 (de) 2001-05-23
JPH06203597A (ja) 1994-07-22
EP0591811A3 (en) 1997-02-12

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