DE69331052D1 - Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess - Google Patents

Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess

Info

Publication number
DE69331052D1
DE69331052D1 DE69331052T DE69331052T DE69331052D1 DE 69331052 D1 DE69331052 D1 DE 69331052D1 DE 69331052 T DE69331052 T DE 69331052T DE 69331052 T DE69331052 T DE 69331052T DE 69331052 D1 DE69331052 D1 DE 69331052D1
Authority
DE
Germany
Prior art keywords
manufacturing process
semiconductor devices
edge structure
voltage semiconductor
associated manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69331052T
Other languages
English (en)
Other versions
DE69331052T2 (de
Inventor
Raffaele Zambrano
Salvatore Leonardi
Giovanna Cacciola
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Application granted granted Critical
Publication of DE69331052D1 publication Critical patent/DE69331052D1/de
Publication of DE69331052T2 publication Critical patent/DE69331052T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
DE69331052T 1993-07-01 1993-07-01 Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess Expired - Fee Related DE69331052T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93830286A EP0632503B1 (de) 1993-07-01 1993-07-01 Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess

Publications (2)

Publication Number Publication Date
DE69331052D1 true DE69331052D1 (de) 2001-12-06
DE69331052T2 DE69331052T2 (de) 2002-06-06

Family

ID=8215196

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69331052T Expired - Fee Related DE69331052T2 (de) 1993-07-01 1993-07-01 Integrierte Randstruktur für Hochspannung-Halbleiteranordnungen und dazugehöriger Herstellungsprozess

Country Status (4)

Country Link
US (2) US5489799A (de)
EP (1) EP0632503B1 (de)
JP (1) JPH07312372A (de)
DE (1) DE69331052T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798554A (en) * 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
DE69531783T2 (de) * 1995-10-09 2004-07-15 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme Herstellungsverfahren für Leistungsanordnung mit Schutzring
JP3062065B2 (ja) * 1995-10-20 2000-07-10 日本電気株式会社 半導体装置の製造方法
DE69534919T2 (de) * 1995-10-30 2007-01-25 Stmicroelectronics S.R.L., Agrate Brianza Leistungsvorrichtung in MOS-Technologie mit einer einzigen kritischen Größe
DE69533134T2 (de) * 1995-10-30 2005-07-07 Stmicroelectronics S.R.L., Agrate Brianza Leistungsbauteil hoher Dichte in MOS-Technologie
DE69515876T2 (de) * 1995-11-06 2000-08-17 St Microelectronics Srl Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
US6228719B1 (en) 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
DE69530216T2 (de) * 1995-12-19 2004-02-12 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno - Corimme Monolithische Halbleiteranordnung mit Randstruktur und Verfahren zur Herstellung
DE69518653T2 (de) * 1995-12-28 2001-04-19 St Microelectronics Srl MOS-Technologie-Leistungsanordnung in integrierter Struktur
DE19631872C2 (de) * 1996-08-07 2003-04-17 Daimler Chrysler Ag Vertikales Halbleiterbauelement
US5936284A (en) * 1997-11-03 1999-08-10 Sgs-Thomson Microelectronics S.R.L. Electrostatic discharge protection circuit and transistor
US6373100B1 (en) 1998-03-04 2002-04-16 Semiconductor Components Industries Llc Semiconductor device and method for fabricating the same
EP0961325B1 (de) 1998-05-26 2008-05-07 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
DE69833743T2 (de) * 1998-12-09 2006-11-09 Stmicroelectronics S.R.L., Agrate Brianza Herstellungmethode einer integrierte Randstruktur für Hochspannung-Halbleiteranordnungen
JP4484979B2 (ja) * 1999-03-19 2010-06-16 セイコーインスツル株式会社 バイポ−ラトランジスタの製造方法
US6225181B1 (en) 1999-04-19 2001-05-01 National Semiconductor Corp. Trench isolated bipolar transistor structure integrated with CMOS technology
US6242784B1 (en) * 1999-06-28 2001-06-05 Intersil Corporation Edge termination for silicon power devices
US6236100B1 (en) * 2000-01-28 2001-05-22 General Electronics Applications, Inc. Semiconductor with high-voltage components and low-voltage components on a shared die
JP2001284632A (ja) * 2000-04-03 2001-10-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3730483B2 (ja) * 2000-06-30 2006-01-05 株式会社東芝 バイポーラトランジスタ
JP4447768B2 (ja) * 2000-12-01 2010-04-07 三菱電機株式会社 フィールドｍｏｓトランジスタおよびそれを含む半導体集積回路
FR2820546B1 (fr) * 2001-02-05 2003-07-11 St Microelectronics Sa Structure de protection contre des parasites
US6797992B2 (en) * 2001-08-07 2004-09-28 Fabtech, Inc. Apparatus and method for fabricating a high reverse voltage semiconductor device
DE102004002181B4 (de) * 2004-01-15 2011-08-18 Infineon Technologies AG, 81669 Integrierter Transistor, insbesondere für Spannungen größer 40 Volt, und Herstellungsverfahren
US8150363B2 (en) 2006-02-16 2012-04-03 Telecommunication Systems, Inc. Enhanced E911 network access for call centers
CN101630683B (zh) 2008-07-15 2011-03-23 中芯国际集成电路制造(上海)有限公司 集成静电放电器件
US9633993B1 (en) * 2016-04-01 2017-04-25 Texas Instruments Incorporated Bipolar SCR
US11273022B2 (en) 2018-02-13 2022-03-15 Emanate Biomedical, Inc. Oral appliance in a blockchain system
CN110010677B (zh) * 2019-04-25 2024-02-13 江苏新顺微电子股份有限公司 一种改善结终端延伸结构三极管可靠性的器件结构及其制造方法
CN111554738A (zh) * 2020-04-29 2020-08-18 杭州士兰微电子股份有限公司 半导体器件及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100744A (en) * 1980-12-15 1982-06-23 Matsushita Electric Works Ltd Manufacture of semiconductor device
FR2543739B1 (fr) * 1983-03-30 1986-04-18 Radiotechnique Compelec Procede de realisation d'un transistor bipolaire haute tension
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
IT1217322B (it) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa Procedimento di fabbricazione di un dispositivo nonolitico a semiconduttope comprendente almeno un transistor di un circuito integrato di comando e un transistor di rotenza in tegrato nella stessa piastrina
JPH0828373B2 (ja) * 1988-12-06 1996-03-21 富士電機株式会社 集積回路装置用接合分離半導体領域構造

Also Published As

Publication number Publication date
US5489799A (en) 1996-02-06
US5895249A (en) 1999-04-20
EP0632503B1 (de) 2001-10-31
JPH07312372A (ja) 1995-11-28
EP0632503A1 (de) 1995-01-04
DE69331052T2 (de) 2002-06-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee