DE69400402T2 - Integrierte Speicherschaltung mit verbesserter Lesezeit - Google Patents

Integrierte Speicherschaltung mit verbesserter Lesezeit

Info

Publication number
DE69400402T2
DE69400402T2 DE69400402T DE69400402T DE69400402T2 DE 69400402 T2 DE69400402 T2 DE 69400402T2 DE 69400402 T DE69400402 T DE 69400402T DE 69400402 T DE69400402 T DE 69400402T DE 69400402 T2 DE69400402 T2 DE 69400402T2
Authority
DE
Germany
Prior art keywords
memory circuit
integrated memory
read time
improved read
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69400402T
Other languages
English (en)
Other versions
DE69400402D1 (de
Inventor
Jean Devin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE69400402D1 publication Critical patent/DE69400402D1/de
Application granted granted Critical
Publication of DE69400402T2 publication Critical patent/DE69400402T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
DE69400402T 1993-12-22 1994-12-16 Integrierte Speicherschaltung mit verbesserter Lesezeit Expired - Fee Related DE69400402T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9315499A FR2714202B1 (fr) 1993-12-22 1993-12-22 Mémoire en circuit intégré à temps de lecture amélioré.

Publications (2)

Publication Number Publication Date
DE69400402D1 DE69400402D1 (de) 1996-09-26
DE69400402T2 true DE69400402T2 (de) 1997-01-23

Family

ID=9454267

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69400402T Expired - Fee Related DE69400402T2 (de) 1993-12-22 1994-12-16 Integrierte Speicherschaltung mit verbesserter Lesezeit

Country Status (5)

Country Link
US (1) US5537349A (de)
EP (1) EP0660333B1 (de)
JP (1) JP2886472B2 (de)
DE (1) DE69400402T2 (de)
FR (1) FR2714202B1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19615407C1 (de) * 1996-04-18 1997-08-21 Siemens Ag Programmierbarer Festwertspeicher mit verbesserter Zugriffszeit
FR2752324B1 (fr) * 1996-08-08 1998-09-18 Sgs Thomson Microelectronics Memoire non volatile en circuit-integre a lecture rapide
FR2755286B1 (fr) * 1996-10-25 1999-01-22 Sgs Thomson Microelectronics Memoire a temps de lecture ameliore
FR2758645B1 (fr) * 1997-01-22 2001-12-14 Sgs Thomson Microelectronics Dispositif et procede de programmation d'une memoire
TW419669B (en) * 1998-03-16 2001-01-21 Nippon Electric Co Semiconductor memory device
US6314049B1 (en) * 2000-03-30 2001-11-06 Micron Technology, Inc. Elimination of precharge operation in synchronous flash memory
US6876582B2 (en) * 2002-05-24 2005-04-05 Hynix Semiconductor, Inc. Flash memory cell erase scheme using both source and channel regions
US6768677B2 (en) * 2002-11-22 2004-07-27 Advanced Micro Devices, Inc. Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage
JP2005190626A (ja) * 2003-12-26 2005-07-14 Sharp Corp 半導体読み出し回路
US8184487B2 (en) * 2010-08-30 2012-05-22 Micron Technology, Inc. Modified read operation for non-volatile memory
IT1404183B1 (it) 2011-02-28 2013-11-15 St Microelectronics Srl Dispositivo di decodifica di indirizzo

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117342A (en) * 1977-03-23 1978-10-13 Nec Corp Memory unit
JPS5963091A (ja) * 1982-09-30 1984-04-10 Fujitsu Ltd スタテイツクメモリ回路
JPS60224197A (ja) * 1984-04-20 1985-11-08 Hitachi Ltd 記憶素子回路およびそれを用いたマイクロコンピュータ
JPS6231094A (ja) * 1985-08-01 1987-02-10 Toshiba Corp 不揮発性半導体記憶装置
JPS62172595A (ja) * 1986-01-24 1987-07-29 Mitsubishi Electric Corp 半導体集積回路記憶装置
JPS62214596A (ja) * 1986-03-14 1987-09-21 Mitsubishi Electric Corp 半導体回路装置
FR2608826B1 (fr) * 1986-12-19 1989-03-17 Eurotechnique Sa Circuit integre comportant des elements d'aiguillage vers des elements de redondance dans une memoire
US5058069A (en) * 1987-03-03 1991-10-15 Thomson Semiconducteurs Device for addressing of redundant elements of an integrated circuit memory
FR2611972B1 (fr) * 1987-03-03 1989-05-19 Thomson Semiconducteurs Procede d'adressage d'elements redondants d'une memoire integree et dispositif permettant de mettre en oeuvre le procede
FR2622038B1 (fr) * 1987-10-19 1990-01-19 Thomson Semiconducteurs Procede de programmation des cellules memoire d'une memoire et circuit pour la mise en oeuvre de ce procede
FR2623651B1 (fr) * 1987-11-20 1992-11-27 Sgs Thomson Microelectronics Plan memoire et procede et prototype de definition d'un circuit integre electronique comportant un tel plan memoire
FR2623653B1 (fr) * 1987-11-24 1992-10-23 Sgs Thomson Microelectronics Procede de test de cellules de memoire electriquement programmable et circuit integre correspondant
FR2630573B1 (fr) * 1988-04-26 1990-07-13 Sgs Thomson Microelectronics Memoire programmable electriquement avec plusieurs bits d'information par cellule
FR2652672B1 (fr) * 1989-10-02 1991-12-20 Sgs Thomson Microelectronics Memoire a temps de lecture ameliore.
FR2659165A1 (fr) * 1990-03-05 1991-09-06 Sgs Thomson Microelectronics Memoire ultra-rapide comportant un limiteur de la tension de drain des cellules.

Also Published As

Publication number Publication date
EP0660333A1 (de) 1995-06-28
FR2714202A1 (fr) 1995-06-23
US5537349A (en) 1996-07-16
EP0660333B1 (de) 1996-08-21
DE69400402D1 (de) 1996-09-26
JP2886472B2 (ja) 1999-04-26
JPH07320493A (ja) 1995-12-08
FR2714202B1 (fr) 1996-01-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee