DE69405438D1 - Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter Schaltungen - Google Patents
Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter SchaltungenInfo
- Publication number
- DE69405438D1 DE69405438D1 DE69405438T DE69405438T DE69405438D1 DE 69405438 D1 DE69405438 D1 DE 69405438D1 DE 69405438 T DE69405438 T DE 69405438T DE 69405438 T DE69405438 T DE 69405438T DE 69405438 D1 DE69405438 D1 DE 69405438D1
- Authority
- DE
- Germany
- Prior art keywords
- formation
- production
- integrated circuits
- oxynitride layers
- dielectric oxynitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3658593A | 1993-03-24 | 1993-03-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69405438D1 true DE69405438D1 (de) | 1997-10-16 |
DE69405438T2 DE69405438T2 (de) | 1998-04-02 |
Family
ID=21889428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69405438T Expired - Lifetime DE69405438T2 (de) | 1993-03-24 | 1994-03-16 | Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter Schaltungen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5464783A (de) |
EP (1) | EP0617461B1 (de) |
JP (1) | JPH06302814A (de) |
DE (1) | DE69405438T2 (de) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726087A (en) * | 1992-04-30 | 1998-03-10 | Motorola, Inc. | Method of formation of semiconductor gate dielectric |
US5508532A (en) * | 1994-06-16 | 1996-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with braded silicon nitride |
JP3305901B2 (ja) * | 1994-12-14 | 2002-07-24 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR0163932B1 (ko) * | 1995-02-24 | 1999-01-15 | 김광호 | 폴리실리콘 박막트랜지스터 액정디스플레이 화소부분의 엘디디 구조 및 그 제조방법 |
JP2871530B2 (ja) * | 1995-05-10 | 1999-03-17 | 日本電気株式会社 | 半導体装置の製造方法 |
JP4001960B2 (ja) * | 1995-11-03 | 2007-10-31 | フリースケール セミコンダクター インコーポレイテッド | 窒化酸化物誘電体層を有する半導体素子の製造方法 |
US5652166A (en) * | 1996-01-11 | 1997-07-29 | United Microelectronics Corporation | Process for fabricating dual-gate CMOS having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition |
KR100207485B1 (ko) * | 1996-07-23 | 1999-07-15 | 윤종용 | 반도체장치의 커패시터 제조방법 |
KR980012639A (ko) * | 1996-07-29 | 1998-04-30 | 윌리엄 비. 켐플러 | 초박 적층형 게이트 유전체 구조물 |
US5939763A (en) * | 1996-09-05 | 1999-08-17 | Advanced Micro Devices, Inc. | Ultrathin oxynitride structure and process for VLSI applications |
US6319857B1 (en) * | 1996-09-16 | 2001-11-20 | Advanced Micro Devices, Inc. | Method of fabricating stacked N-O-N ultrathin gate dielectric structures |
US5969397A (en) * | 1996-11-26 | 1999-10-19 | Texas Instruments Incorporated | Low defect density composite dielectric |
US5960302A (en) * | 1996-12-31 | 1999-09-28 | Lucent Technologies, Inc. | Method of making a dielectric for an integrated circuit |
US6048769A (en) | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
JP3949211B2 (ja) * | 1997-03-06 | 2007-07-25 | 富士通株式会社 | 半導体装置の製造方法 |
JPH10313114A (ja) * | 1997-05-14 | 1998-11-24 | Nec Corp | 半導体装置の製造方法 |
US5998270A (en) * | 1997-05-15 | 1999-12-07 | Advanced Micro Devices | Formation of oxynitride and polysilicon layers in a single reaction chamber |
US6184083B1 (en) * | 1997-06-30 | 2001-02-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US5969382A (en) | 1997-11-03 | 1999-10-19 | Delco Electronics Corporation | EPROM in high density CMOS having added substrate diffusion |
US5972804A (en) * | 1997-08-05 | 1999-10-26 | Motorola, Inc. | Process for forming a semiconductor device |
US6566281B1 (en) * | 1997-10-15 | 2003-05-20 | International Business Machines Corporation | Nitrogen-rich barrier layer and structures formed |
US5834353A (en) * | 1997-10-20 | 1998-11-10 | Texas Instruments-Acer Incorporated | Method of making deep sub-micron meter MOSFET with a high permitivity gate dielectric |
US6087229A (en) * | 1998-03-09 | 2000-07-11 | Lsi Logic Corporation | Composite semiconductor gate dielectrics |
US6033998A (en) * | 1998-03-09 | 2000-03-07 | Lsi Logic Corporation | Method of forming variable thickness gate dielectrics |
US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
JP3472482B2 (ja) | 1998-06-30 | 2003-12-02 | 富士通株式会社 | 半導体装置の製造方法と製造装置 |
US6274442B1 (en) * | 1998-07-15 | 2001-08-14 | Advanced Micro Devices, Inc. | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
US6162687A (en) * | 1998-08-19 | 2000-12-19 | Advanced Micro Devices, Inc. | Method of manufacturing semiconductor device having oxide-nitride gate insulating layer |
US6114258A (en) * | 1998-10-19 | 2000-09-05 | Applied Materials, Inc. | Method of oxidizing a substrate in the presence of nitride and oxynitride films |
US6087236A (en) * | 1998-11-24 | 2000-07-11 | Intel Corporation | Integrated circuit with multiple gate dielectric structures |
US6228724B1 (en) * | 1999-01-28 | 2001-05-08 | Advanced Mirco Devices | Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby |
US6566181B2 (en) * | 1999-02-26 | 2003-05-20 | Agere Systems Inc. | Process for the fabrication of dual gate structures for CMOS devices |
US6261976B1 (en) | 1999-03-18 | 2001-07-17 | Chartered Semiconductor Manufacturing Ltd. | Method of forming low pressure silicon oxynitride dielectrics having high reliability |
US6551946B1 (en) | 1999-06-24 | 2003-04-22 | Agere Systems Inc. | Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature |
US6492712B1 (en) * | 1999-06-24 | 2002-12-10 | Agere Systems Guardian Corp. | High quality oxide for use in integrated circuits |
US20030235957A1 (en) * | 2002-06-25 | 2003-12-25 | Samir Chaudhry | Method and structure for graded gate oxides on vertical and non-planar surfaces |
US7081419B2 (en) * | 2000-06-28 | 2006-07-25 | Agere Systems Inc. | Gate dielectric structure for reducing boron penetration and current leakage |
JP3746669B2 (ja) * | 2000-10-17 | 2006-02-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6613695B2 (en) | 2000-11-24 | 2003-09-02 | Asm America, Inc. | Surface preparation prior to deposition |
US6709928B1 (en) * | 2001-07-31 | 2004-03-23 | Cypress Semiconductor Corporation | Semiconductor device having silicon-rich layer and method of manufacturing such a device |
US6642156B2 (en) * | 2001-08-01 | 2003-11-04 | International Business Machines Corporation | Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics |
US7129128B2 (en) * | 2001-08-29 | 2006-10-31 | Micron Technology, Inc. | Method of improved high K dielectric-polysilicon interface for CMOS devices |
US6960537B2 (en) | 2001-10-02 | 2005-11-01 | Asm America, Inc. | Incorporation of nitrogen into high k dielectric film |
US7358198B2 (en) * | 2002-03-08 | 2008-04-15 | Kabushiki Kaisha Toshiba | Semiconductor device and method for fabricating same |
JP2003264190A (ja) * | 2002-03-08 | 2003-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4173672B2 (ja) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6878415B2 (en) * | 2002-04-15 | 2005-04-12 | Varian Semiconductor Equipment Associates, Inc. | Methods for chemical formation of thin film layers using short-time thermal processes |
US7067439B2 (en) | 2002-06-14 | 2006-06-27 | Applied Materials, Inc. | ALD metal oxide deposition process using direct oxidation |
JP3538679B2 (ja) * | 2002-06-24 | 2004-06-14 | 沖電気工業株式会社 | 電界効果型トランジスタの製造方法 |
US7022625B2 (en) * | 2002-07-25 | 2006-04-04 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration |
US7214991B2 (en) * | 2002-12-06 | 2007-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS inverters configured using multiple-gate transistors |
US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
US6838396B2 (en) * | 2003-03-28 | 2005-01-04 | International Business Machines Corporation | Bilayer ultra-thin gate dielectric and process for semiconductor metal contamination reduction |
US7074656B2 (en) * | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
US7005330B2 (en) * | 2003-06-27 | 2006-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming the gate electrode in a multiple-gate transistor |
US8119210B2 (en) | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
US7452778B2 (en) * | 2004-06-10 | 2008-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-wire devices and methods of fabrication |
US20060276014A1 (en) * | 2005-06-07 | 2006-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned high-energy implantation for deep junction structure |
KR100668222B1 (ko) * | 2005-06-13 | 2007-01-11 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자의 적층 게이트 구조 및 그 형성 방법 |
US7837838B2 (en) | 2006-03-09 | 2010-11-23 | Applied Materials, Inc. | Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus |
US7645710B2 (en) | 2006-03-09 | 2010-01-12 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
US7678710B2 (en) | 2006-03-09 | 2010-03-16 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
TWI435376B (zh) | 2006-09-26 | 2014-04-21 | Applied Materials Inc | 用於缺陷鈍化之高k閘極堆疊的氟電漿處理 |
US8067284B1 (en) | 2007-05-25 | 2011-11-29 | Cypress Semiconductor Corporation | Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8283261B2 (en) * | 2007-05-25 | 2012-10-09 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US8643124B2 (en) | 2007-05-25 | 2014-02-04 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US7898852B1 (en) | 2007-12-27 | 2011-03-01 | Cypress Semiconductor Corporation | Trapped-charge non-volatile memory with uniform multilevel programming |
US8088683B2 (en) * | 2008-03-31 | 2012-01-03 | Cypress Semiconductor Corporation | Sequential deposition and anneal of a dielectic layer in a charge trapping memory device |
US9147613B2 (en) | 2010-05-07 | 2015-09-29 | Intersil Americas LLC | Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom |
US20120276730A1 (en) * | 2011-04-27 | 2012-11-01 | Nanya Technology Corporation | Methods for fabricating a gate dielectric layer and for fabricating a gate structure |
US8685813B2 (en) | 2012-02-15 | 2014-04-01 | Cypress Semiconductor Corporation | Method of integrating a charge-trapping gate stack into a CMOS flow |
US11061244B2 (en) | 2016-04-28 | 2021-07-13 | Mitsubishi Electric Corporation | Collimated light generating apparatus |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3558348A (en) * | 1968-04-18 | 1971-01-26 | Bell Telephone Labor Inc | Dielectric films for semiconductor devices |
US3765935A (en) * | 1971-08-10 | 1973-10-16 | Bell Telephone Labor Inc | Radiation resistant coatings for semiconductor devices |
EP0072603B1 (de) * | 1978-06-14 | 1986-10-01 | Fujitsu Limited | Verfahren zur Herstellung einer Halbleiteranordnung mit einer Isolierschicht aus Siliziumdioxid, die mit einer Schicht aus Siliziumoxynitrid bedeckt ist |
JPS5642377A (en) * | 1979-09-14 | 1981-04-20 | Fujitsu Ltd | Ultraviolet ray erasable type rewritable read-only memory |
JPS5693344A (en) * | 1979-12-26 | 1981-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
US4438157A (en) * | 1980-12-05 | 1984-03-20 | Ncr Corporation | Process for forming MNOS dual dielectric structure |
US4490900A (en) * | 1982-01-29 | 1985-01-01 | Seeq Technology, Inc. | Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein |
WO1984000852A1 (en) * | 1982-08-12 | 1984-03-01 | Ncr Co | Non-volatile semiconductor memory device |
US4725560A (en) * | 1986-09-08 | 1988-02-16 | International Business Machines Corp. | Silicon oxynitride storage node dielectric |
JP2664685B2 (ja) * | 1987-07-31 | 1997-10-15 | 株式会社東芝 | 半導体装置の製造方法 |
US4851370A (en) * | 1987-12-28 | 1989-07-25 | American Telephone And Telegraph Company, At&T Bell Laboratories | Fabricating a semiconductor device with low defect density oxide |
US4937756A (en) * | 1988-01-15 | 1990-06-26 | Industrial Technology Research Institute | Gated isolated structure |
US5013692A (en) * | 1988-12-08 | 1991-05-07 | Sharp Kabushiki Kaisha | Process for preparing a silicon nitride insulating film for semiconductor memory device |
US5198392A (en) * | 1989-11-20 | 1993-03-30 | Oki Electric Industry Co., Ltd. | Method of forming a nitrided silicon dioxide (SiOx Ny) film |
US5219773A (en) * | 1990-06-26 | 1993-06-15 | Massachusetts Institute Of Technology | Method of making reoxidized nitrided oxide MOSFETs |
KR940009597B1 (ko) * | 1991-08-22 | 1994-10-15 | 삼성전자 주식회사 | 반도체장치의 게이트산화막 형성법 |
US5244843A (en) * | 1991-12-17 | 1993-09-14 | Intel Corporation | Process for forming a thin oxide layer |
-
1994
- 1994-03-16 DE DE69405438T patent/DE69405438T2/de not_active Expired - Lifetime
- 1994-03-16 EP EP94301896A patent/EP0617461B1/de not_active Expired - Lifetime
- 1994-03-24 JP JP6052372A patent/JPH06302814A/ja active Pending
-
1995
- 1995-02-02 US US08/382,956 patent/US5464783A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0617461A3 (de) | 1995-01-11 |
EP0617461A2 (de) | 1994-09-28 |
DE69405438T2 (de) | 1998-04-02 |
EP0617461B1 (de) | 1997-09-10 |
US5464783A (en) | 1995-11-07 |
JPH06302814A (ja) | 1994-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69405438T2 (de) | Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter Schaltungen | |
DE69116058D1 (de) | Verfahren zur Herstellung integrierter Schaltungen | |
DE68929012D1 (de) | Verfahren zur Herstellung von Mehrschichtschaltungen | |
DE69431573T2 (de) | Verfahren zur Herstellung von Schichten | |
DE69204571T2 (de) | Verfahren zur Herstellung von elektronischen Mehrschichtschaltungen. | |
DE69617147D1 (de) | Verfahren zur Herstellung dünner Halbleiterschichten | |
DE69410301T2 (de) | Verfahren zur Herstellung funktioneller niedergeschlagener Schichten | |
DE69434536D1 (de) | Verfahren zur Herstellung von halbleitenden Wafern | |
DE69309634T2 (de) | Verfahren zur Herstellung von Siliciumdioxidschichten | |
DE69723338D1 (de) | Verfahren zur Herstellung von Halbleiterscheiben | |
DE69622928T2 (de) | Verfahren zur Herstellung von Schutzschichten aus Siliziumdioxid | |
DE69429978T2 (de) | Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen | |
DE69307944T2 (de) | Verfahren zur Herstellung von Substraten für gedruckte Schaltungen | |
DE69504563D1 (de) | Verfahren zur Herstellung von Dünnschichten | |
DE69703600T2 (de) | Verfahren zur Herstellung von Halbleiterscheiben | |
DE69930102D1 (de) | Verfahren zur herstellung von integrierten schaltungen | |
DE69701822D1 (de) | Verfahren zur Herstellung von Polyalkoholen | |
DE59402721D1 (de) | Verfahren zur Herstellung von PZT-Schichten | |
DE69033940D1 (de) | Verfahren zur Herstellung vergrabener Zonen für integrierte Schaltungen | |
DE69228525D1 (de) | Verfahren zur Bildung von Siliziden bei der Herstellung von integrierten Schaltungen | |
DE69818953D1 (de) | Verfahren und Lösung zum Ätzen von Trimetallschichten zur Herstellung von elektronischen Schaltungen | |
DE69329999T2 (de) | Verfahren zur Herstellung integrierter Schaltungen, insbesondere intelligenter Leistungsanordnungen | |
DE59700009D1 (de) | Verfahren zur Herstellung von Halbleiterscheiben | |
DE69431389D1 (de) | Verfahren zur Herstellung von Isolationszonen für integrierte Schaltungen | |
DE69323859T2 (de) | Verfahren zur Herstellung einer isolierten Schicht |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |