DE69411292T2 - Programmierbare logische Schaltung - Google Patents

Programmierbare logische Schaltung

Info

Publication number
DE69411292T2
DE69411292T2 DE69411292T DE69411292T DE69411292T2 DE 69411292 T2 DE69411292 T2 DE 69411292T2 DE 69411292 T DE69411292 T DE 69411292T DE 69411292 T DE69411292 T DE 69411292T DE 69411292 T2 DE69411292 T2 DE 69411292T2
Authority
DE
Germany
Prior art keywords
logic circuit
programmable logic
programmable
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69411292T
Other languages
English (en)
Other versions
DE69411292D1 (de
Inventor
Anthony Ian Stansfield
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHANCELLOR
University of Oxford
STMicroelectronics Ltd Great Britain
Original Assignee
CHANCELLOR
University of Oxford
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHANCELLOR, University of Oxford, SGS Thomson Microelectronics Ltd filed Critical CHANCELLOR
Publication of DE69411292D1 publication Critical patent/DE69411292D1/de
Application granted granted Critical
Publication of DE69411292T2 publication Critical patent/DE69411292T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
DE69411292T 1993-02-16 1994-02-09 Programmierbare logische Schaltung Expired - Fee Related DE69411292T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB939303084A GB9303084D0 (en) 1993-02-16 1993-02-16 Programmable logic circuit

Publications (2)

Publication Number Publication Date
DE69411292D1 DE69411292D1 (de) 1998-08-06
DE69411292T2 true DE69411292T2 (de) 1999-01-07

Family

ID=10730517

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69411292T Expired - Fee Related DE69411292T2 (de) 1993-02-16 1994-02-09 Programmierbare logische Schaltung
DE69427241T Expired - Lifetime DE69427241D1 (de) 1993-02-16 1994-02-09 Programmierbare logische Schaltung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69427241T Expired - Lifetime DE69427241D1 (de) 1993-02-16 1994-02-09 Programmierbare logische Schaltung

Country Status (5)

Country Link
US (2) US5408434A (de)
EP (2) EP0612154B1 (de)
JP (1) JPH0758630A (de)
DE (2) DE69411292T2 (de)
GB (1) GB9303084D0 (de)

Families Citing this family (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
DE19501226A1 (de) * 1994-03-25 1995-10-05 Hewlett Packard Co Feldprogrammierbares Gatterarray-Element zur Implementierung von Registerdateien und Assoziativspeichern
US5442306A (en) * 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
US6049223A (en) * 1995-03-22 2000-04-11 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5734582A (en) * 1995-12-12 1998-03-31 International Business Machines Corporation Method and system for layout and schematic generation for heterogeneous arrays
US5719889A (en) * 1995-12-20 1998-02-17 International Business Machines Corporation Programmable parity checking and comparison circuit
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US5760602A (en) * 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
US5977791A (en) 1996-04-15 1999-11-02 Altera Corporation Embedded memory block with FIFO mode for programmable logic device
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US5909125A (en) * 1996-12-24 1999-06-01 Xilinx, Inc. FPGA using RAM control signal lines as routing or logic resources after configuration
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US6029236A (en) * 1997-01-28 2000-02-22 Altera Corporation Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
EP0863515B1 (de) * 1997-03-05 2004-05-26 STMicroelectronics S.r.l. Verbindungskoppelmatrix für integrierte Halbleitermikrokontrollerschaltung
US6020759A (en) 1997-03-21 2000-02-01 Altera Corporation Programmable logic array device with random access memory configurable as product terms
US6160419A (en) * 1997-11-03 2000-12-12 Altera Corporation Programmable logic architecture incorporating a content addressable embedded array block
US5940852A (en) * 1997-05-01 1999-08-17 Altera Corporation Memory cells configurable as CAM or RAM in programmable logic devices
US6181159B1 (en) 1997-05-06 2001-01-30 Altera Corporation Integrated circuit incorporating a programmable cross-bar switch
US6006321A (en) * 1997-06-13 1999-12-21 Malleable Technologies, Inc. Programmable logic datapath that may be used in a field programmable device
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6034857A (en) * 1997-07-16 2000-03-07 Altera Corporation Input/output buffer with overcurrent protection circuit
US6011744A (en) 1997-07-16 2000-01-04 Altera Corporation Programmable logic device with multi-port memory
US6263400B1 (en) * 1997-08-21 2001-07-17 Altera Corporation Memory cells configurable as CAM or RAM in programmable logic devices
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US5999104A (en) * 1997-12-03 1999-12-07 Ford Motor Company Method of producing customizable automotive electronic systems
US6005488A (en) * 1997-12-03 1999-12-21 Ford Motor Company User control interface architecture for automotive electronic systems
US6046603A (en) * 1997-12-12 2000-04-04 Xilinx, Inc. Method and apparatus for controlling the partial reconfiguration of a field programmable gate array
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6147890A (en) * 1997-12-30 2000-11-14 Kawasaki Steel Corporation FPGA with embedded content-addressable memory
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
KR100250807B1 (ko) * 1998-02-26 2000-05-01 윤덕용 캠 셀 구조 및 캠 셀을 이용한 필드 컨피규어러블 램과 프로그래머블 로직어레이 겸용 메모리
US6467017B1 (en) 1998-06-23 2002-10-15 Altera Corporation Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6144573A (en) 1998-06-26 2000-11-07 Altera Corporation Programmable logic devices with improved content addressable memory capabilities
US6453382B1 (en) 1998-11-05 2002-09-17 Altera Corporation Content addressable memory encoded outputs
US6114873A (en) * 1998-12-17 2000-09-05 Nortel Networks Corporation Content addressable memory programmable array
DE19860390A1 (de) * 1998-12-28 2000-06-29 Deutsche Telekom Ag Programmierbarer Logikbaustein und Verfahren zur Dekodierung von Daten
US6262933B1 (en) 1999-01-29 2001-07-17 Altera Corporation High speed programmable address decoder
JP3269526B2 (ja) 1999-02-09 2002-03-25 日本電気株式会社 プログラマブルロジックｌｓｉ
US6150838A (en) 1999-02-25 2000-11-21 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
US6184712B1 (en) 1999-02-25 2001-02-06 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
US6400180B2 (en) 1999-02-25 2002-06-04 Xilinix, Inc. Configurable lookup table for programmable logic devices
US6396302B2 (en) 1999-02-25 2002-05-28 Xilinx, Inc. Configurable logic element with expander structures
US6157211A (en) 1999-04-14 2000-12-05 Xilinx, Inc. FPGA using RAM control signal lines as routing or logic resources after configuration
SE518883C2 (sv) 1999-05-19 2002-12-03 Switchcore Ab Cam/ram-minnesanordning med en skalbar struktur
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US6486702B1 (en) 1999-07-02 2002-11-26 Altera Corporation Embedded memory blocks for programmable logic
US6134135A (en) * 2000-01-10 2000-10-17 Switchcore, A.B. Mask arrangement for scalable CAM/RAM structures
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US6605962B2 (en) 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US7076595B1 (en) 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
EP1402382B1 (de) 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7167471B2 (en) * 2001-08-28 2007-01-23 International Business Machines Corporation Network processor with single interface supporting tree search engine and CAM
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7420392B2 (en) * 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US6781407B2 (en) 2002-01-09 2004-08-24 Xilinx, Inc. FPGA and embedded circuitry initialization and processing
US6798239B2 (en) * 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6996758B1 (en) 2001-11-16 2006-02-07 Xilinx, Inc. Apparatus for testing an interconnecting logic fabric
US6983405B1 (en) 2001-11-16 2006-01-03 Xilinx, Inc., Method and apparatus for testing circuitry embedded within a field programmable gate array
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
WO2003071432A2 (de) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US6976160B1 (en) 2002-02-22 2005-12-13 Xilinx, Inc. Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US6754882B1 (en) 2002-02-22 2004-06-22 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US6693452B1 (en) * 2002-02-25 2004-02-17 Xilinx, Inc. Floor planning for programmable gate array having embedded fixed logic circuitry
US7007121B1 (en) 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US6839874B1 (en) 2002-02-28 2005-01-04 Xilinx, Inc. Method and apparatus for testing an embedded device
US7111217B1 (en) 2002-02-28 2006-09-19 Xilinx, Inc. Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
US7111220B1 (en) 2002-03-01 2006-09-19 Xilinx, Inc. Network physical layer with embedded multi-standard CRC generator
US7187709B1 (en) 2002-03-01 2007-03-06 Xilinx, Inc. High speed configurable transceiver architecture
US7088767B1 (en) 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US6961919B1 (en) 2002-03-04 2005-11-01 Xilinx, Inc. Method of designing integrated circuit having both configurable and fixed logic circuitry
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6973405B1 (en) 2002-05-22 2005-12-06 Xilinx, Inc. Programmable interactive verification agent
US6772405B1 (en) 2002-06-13 2004-08-03 Xilinx, Inc. Insertable block tile for interconnecting to a device embedded in an integrated circuit
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7099426B1 (en) 2002-09-03 2006-08-29 Xilinx, Inc. Flexible channel bonding and clock correction operations on a multi-block data path
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7092865B1 (en) 2002-09-10 2006-08-15 Xilinx, Inc. Method and apparatus for timing modeling
US7111110B1 (en) 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
US6982891B2 (en) * 2003-06-10 2006-01-03 Lsi Logic Corporation Re-configurable content addressable/dual port memory
EP1676208A2 (de) 2003-08-28 2006-07-05 PACT XPP Technologies AG Datenverarbeitungseinrichtung und verfahren
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
US7595655B2 (en) * 2007-06-27 2009-09-29 Tabula, Inc. Retrieving data from a configurable IC
US8645620B2 (en) * 2007-06-29 2014-02-04 International Business Machines Corporation Apparatus and method for accessing a memory device
WO2010016857A1 (en) * 2008-08-04 2010-02-11 Tabula, Inc. Trigger circuits and event counters for an ic
US20100057685A1 (en) * 2008-09-02 2010-03-04 Qimonda Ag Information storage and retrieval system
US7821295B1 (en) 2009-03-27 2010-10-26 Altera Corporation Methods and systems for improving a maximum operating frequency of a PLD having a shift register within an embedded memory block
US8191028B1 (en) 2009-04-07 2012-05-29 Altera Corporation Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
US8868820B2 (en) * 2011-10-31 2014-10-21 Microsemi SoC Corporation RAM block designed for efficient ganging
WO2013071183A1 (en) 2011-11-11 2013-05-16 Tabula, Inc. Content addressable memory in integrated circuit
FI124397B (en) 2013-01-04 2014-08-15 Tellabs Oy A method and apparatus for defining a paging system for a network element of a software configurable network
FI124398B (en) 2013-01-04 2014-08-15 Tellabs Oy A method and apparatus for determining a lookup table implementation for a network element of a software configurable network
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
US9779785B2 (en) * 2015-05-11 2017-10-03 Wisconsin Alumni Research Foundation Computer architecture using compute/storage tiles

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136097A (ja) * 1983-12-23 1985-07-19 Hitachi Ltd 連想メモリ装置
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US4831573A (en) * 1987-03-06 1989-05-16 Altera Corporation Programmable integrated circuit micro-sequencer device
JPH01125124A (ja) * 1987-11-10 1989-05-17 Nec Corp プログラマブル論理アレイ
JP2541248B2 (ja) * 1987-11-20 1996-10-09 三菱電機株式会社 プログラマブル・ロジック・アレイ
US4896060A (en) * 1988-10-31 1990-01-23 Sgs-Thomson Microelectronics, Inc. Dialer with internal option select circuit programmed with externally hardwired address
GB8906145D0 (en) * 1989-03-17 1989-05-04 Algotronix Ltd Configurable cellular array
US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
JPH0654873B2 (ja) * 1989-09-04 1994-07-20 株式会社東芝 プログラマブル型論理装置
US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
US5051949A (en) * 1989-11-15 1991-09-24 Harris Corporation Content addressable memory device
JP2544020B2 (ja) * 1990-11-19 1996-10-16 川崎製鉄株式会社 プログラマブル論理素子
US5388065A (en) * 1991-05-16 1995-02-07 Kawasaki Steel Corporation Semiconductor integrated circuit
US5414377A (en) * 1992-12-21 1995-05-09 Xilinx, Inc. Logic block with look-up table for configuration and memory
US5299147A (en) * 1993-02-22 1994-03-29 Intergraph Corporation Decoder scheme for fully associative translation-lookaside buffer
US5381058A (en) * 1993-05-21 1995-01-10 At&T Corp. FPGA having PFU with programmable output driver inputs

Also Published As

Publication number Publication date
DE69411292D1 (de) 1998-08-06
JPH0758630A (ja) 1995-03-03
EP0612154B1 (de) 1998-07-01
DE69427241D1 (de) 2001-06-21
GB9303084D0 (en) 1993-03-31
EP0836281B1 (de) 2001-05-16
EP0836281A1 (de) 1998-04-15
EP0612154A1 (de) 1994-08-24
US5408434A (en) 1995-04-18
US5473267A (en) 1995-12-05

Similar Documents

Publication Publication Date Title
DE69427241D1 (de) Programmierbare logische Schaltung
DE68917235T2 (de) Programmierbare logische Schaltung.
DE69122065D1 (de) Programmierbare integrierte Schaltung
DE69711794D1 (de) Logik-Auswahlschaltung
DE69133327D1 (de) Programmierbare logische Schaltung
DE69615987T2 (de) Integrierte Schaltung mit programmierbarer Bus-Konfiguration
DE69415592D1 (de) Sicherung
DE69306131D1 (de) Komplementäre logische Schaltung
DE69427339D1 (de) Begrenzungsschaltung
DE69507425D1 (de) Programmierbare pull-up Pufferschaltung
DE69227144D1 (de) Programmierbare logische Einheit
DE69410836D1 (de) Schaltkreis
BR9400988A (pt) Fusível
DE69429409T2 (de) BICMOS-Logikschaltung
DE69122184D1 (de) Schwellenfreie logische Schaltung
DE69320228D1 (de) ODER-Verdrahtete logische Schaltung
DE9404638U1 (de) Programmierbare Schaltungsanordnung
DE69424012D1 (de) Programmierbare logic Array
DE69313257D1 (de) Schaltung
DE9410229U1 (de) Programmierbares Logikmodul
DE9309825U1 (de) Schaltungsanordnung
DE9410437U1 (de) Schmelzsicherung
KR950021818U (ko) 테스트 논리회로
KR930012326U (ko) 씨모스 논리회로
KR950004956U (ko) 채배회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee