DE69414641T2 - Verfahren zur Herstellung einer harzversiegelten Halbleitervorrichtung, bei diesem Verfahren verwendeter Leiterrahmen zur Montage vieler Halbleiterelemente und harzversiegelte Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer harzversiegelten Halbleitervorrichtung, bei diesem Verfahren verwendeter Leiterrahmen zur Montage vieler Halbleiterelemente und harzversiegelte Halbleitervorrichtung

Info

Publication number
DE69414641T2
DE69414641T2 DE69414641T DE69414641T DE69414641T2 DE 69414641 T2 DE69414641 T2 DE 69414641T2 DE 69414641 T DE69414641 T DE 69414641T DE 69414641 T DE69414641 T DE 69414641T DE 69414641 T2 DE69414641 T2 DE 69414641T2
Authority
DE
Germany
Prior art keywords
semiconductor device
resin sealed
sealed semiconductor
manufacturing
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69414641T
Other languages
English (en)
Other versions
DE69414641D1 (de
Inventor
Ryuji Hosokawa
Satoru Yanagida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69414641D1 publication Critical patent/DE69414641D1/de
Application granted granted Critical
Publication of DE69414641T2 publication Critical patent/DE69414641T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
DE69414641T 1993-06-14 1994-03-17 Verfahren zur Herstellung einer harzversiegelten Halbleitervorrichtung, bei diesem Verfahren verwendeter Leiterrahmen zur Montage vieler Halbleiterelemente und harzversiegelte Halbleitervorrichtung Expired - Fee Related DE69414641T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5141790A JP2960283B2 (ja) 1993-06-14 1993-06-14 樹脂封止型半導体装置の製造方法と、この製造方法に用いられる複数の半導体素子を載置するためのリードフレームと、この製造方法によって製造される樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
DE69414641D1 DE69414641D1 (de) 1998-12-24
DE69414641T2 true DE69414641T2 (de) 1999-07-08

Family

ID=15300216

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69414641T Expired - Fee Related DE69414641T2 (de) 1993-06-14 1994-03-17 Verfahren zur Herstellung einer harzversiegelten Halbleitervorrichtung, bei diesem Verfahren verwendeter Leiterrahmen zur Montage vieler Halbleiterelemente und harzversiegelte Halbleitervorrichtung

Country Status (5)

Country Link
US (2) US5543658A (de)
EP (1) EP0630047B1 (de)
JP (1) JP2960283B2 (de)
KR (1) KR0163079B1 (de)
DE (1) DE69414641T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3364044B2 (ja) * 1995-02-07 2003-01-08 三菱電機株式会社 半導体装置の製造装置および半導体装置の製造方法
FR2732509B1 (fr) * 1995-03-31 1997-06-13 Sgs Thomson Microelectronics Boitier de montage d'une puce de circuit integre
KR100186309B1 (ko) * 1996-05-17 1999-03-20 문정환 적층형 버텀 리드 패키지
JP3870301B2 (ja) * 1996-06-11 2007-01-17 ヤマハ株式会社 半導体装置の組立法、半導体装置及び半導体装置の連続組立システム
US5923959A (en) * 1997-07-23 1999-07-13 Micron Technology, Inc. Ball grid array (BGA) encapsulation mold
US6472252B2 (en) * 1997-07-23 2002-10-29 Micron Technology, Inc. Methods for ball grid array (BGA) encapsulation mold
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
US6117382A (en) 1998-02-05 2000-09-12 Micron Technology, Inc. Method for encasing array packages
JP3862410B2 (ja) * 1998-05-12 2006-12-27 三菱電機株式会社 半導体装置の製造方法及びその構造
US6329705B1 (en) 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
TW434756B (en) * 1998-06-01 2001-05-16 Hitachi Ltd Semiconductor device and its manufacturing method
US6122822A (en) * 1998-06-23 2000-09-26 Vanguard International Semiconductor Corporation Method for balancing mold flow in encapsulating devices
MY133357A (en) * 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
US6303981B1 (en) * 1999-09-01 2001-10-16 Micron Technology, Inc. Semiconductor package having stacked dice and leadframes and method of fabrication
JP3733114B2 (ja) * 2000-07-25 2006-01-11 株式会社メヂアナ電子 プラスチックパッケージベース及びエアキャビティ型パッケージ
US20030107120A1 (en) * 2001-12-11 2003-06-12 International Rectifier Corporation Intelligent motor drive module with injection molded package
US20040042183A1 (en) * 2002-09-04 2004-03-04 Alcaria Vicente D. Flex circuit package
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6929485B1 (en) * 2004-03-16 2005-08-16 Agilent Technologies, Inc. Lead frame with interdigitated pins
US20070029648A1 (en) * 2005-08-02 2007-02-08 Texas Instruments Incorporated Enhanced multi-die package
JP4860442B2 (ja) * 2006-11-20 2012-01-25 ローム株式会社 半導体装置
US7642638B2 (en) * 2006-12-22 2010-01-05 United Test And Assembly Center Ltd. Inverted lead frame in substrate
JP4554644B2 (ja) * 2007-06-25 2010-09-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN101359602B (zh) * 2007-08-03 2010-06-09 台湾半导体股份有限公司 单片折叠式表面粘着半导体组件组装方法
US9147649B2 (en) * 2008-01-24 2015-09-29 Infineon Technologies Ag Multi-chip module
US8198710B2 (en) * 2008-02-05 2012-06-12 Fairchild Semiconductor Corporation Folded leadframe multiple die package
US8172360B2 (en) * 2008-02-27 2012-05-08 Hewlett-Packard Development Company, L.P. Printhead servicing system and method
JP5566181B2 (ja) * 2010-05-14 2014-08-06 三菱電機株式会社 パワー半導体モジュールとその製造方法
KR101151561B1 (ko) * 2010-06-17 2012-05-30 유춘환 반도체 장치용 리드 프레임의 접합방법
CN103187317B (zh) * 2011-12-31 2015-08-05 百容电子股份有限公司 半导体元件的组装方法
JP6661565B2 (ja) 2017-03-21 2020-03-11 株式会社東芝 半導体装置及びその製造方法
EP4135028A1 (de) * 2021-08-12 2023-02-15 Murata Manufacturing Co., Ltd. Elektronisches bauteil mit gegossenem gehäuse

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496965A (en) * 1981-05-18 1985-01-29 Texas Instruments Incorporated Stacked interdigitated lead frame assembly
US4446375A (en) * 1981-10-14 1984-05-01 General Electric Company Optocoupler having folded lead frame construction
US5049527A (en) * 1985-06-25 1991-09-17 Hewlett-Packard Company Optical isolator
US4633582A (en) * 1985-08-14 1987-01-06 General Instrument Corporation Method for assembling an optoisolator and leadframe therefor
JPS6344750A (ja) * 1986-08-12 1988-02-25 Shinko Electric Ind Co Ltd 樹脂封止型半導体装置の製造方法およびこれに用いるリ−ドフレ−ム
JPH01257361A (ja) * 1988-04-07 1989-10-13 Nec Corp 樹脂封止型半導体装置
JPH0778596B2 (ja) * 1988-08-19 1995-08-23 富士写真フイルム株式会社 ハロゲン化銀写真乳剤の製造方法
JPH02105450A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体装置
JPH02184054A (ja) * 1989-01-11 1990-07-18 Toshiba Corp ハイブリッド型樹脂封止半導体装置
JPH0793400B2 (ja) * 1990-03-06 1995-10-09 株式会社東芝 半導体装置
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
JP2917575B2 (ja) * 1991-05-23 1999-07-12 株式会社日立製作所 樹脂封止型半導体装置
JPH05144991A (ja) * 1991-11-25 1993-06-11 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
KR950001854A (ko) 1995-01-04
US5614441A (en) 1997-03-25
KR0163079B1 (ko) 1998-12-01
EP0630047B1 (de) 1998-11-18
US5543658A (en) 1996-08-06
DE69414641D1 (de) 1998-12-24
JP2960283B2 (ja) 1999-10-06
EP0630047A1 (de) 1994-12-21
JPH06350011A (ja) 1994-12-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8339 Ceased/non-payment of the annual fee