DE69424523D1 - Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern - Google Patents

Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern

Info

Publication number
DE69424523D1
DE69424523D1 DE69424523T DE69424523T DE69424523D1 DE 69424523 D1 DE69424523 D1 DE 69424523D1 DE 69424523 T DE69424523 T DE 69424523T DE 69424523 T DE69424523 T DE 69424523T DE 69424523 D1 DE69424523 D1 DE 69424523D1
Authority
DE
Germany
Prior art keywords
circuit
control method
internal clock
clock control
programmable memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69424523T
Other languages
English (en)
Other versions
DE69424523T2 (de
Inventor
Luigi Pascucci
Marco Olivo
Carla Maria Golla
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69424523D1 publication Critical patent/DE69424523D1/de
Application granted granted Critical
Publication of DE69424523T2 publication Critical patent/DE69424523T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
DE69424523T 1994-02-18 1994-02-18 Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern Expired - Fee Related DE69424523T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830070A EP0668592B1 (de) 1994-02-18 1994-02-18 Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern

Publications (2)

Publication Number Publication Date
DE69424523D1 true DE69424523D1 (de) 2000-06-21
DE69424523T2 DE69424523T2 (de) 2001-01-18

Family

ID=8218382

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424523T Expired - Fee Related DE69424523T2 (de) 1994-02-18 1994-02-18 Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern

Country Status (4)

Country Link
US (1) US5663921A (de)
EP (1) EP0668592B1 (de)
JP (1) JP3011042B2 (de)
DE (1) DE69424523T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920518A (en) 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5959935A (en) * 1997-05-30 1999-09-28 Sgs-Thomson Microelectronics S.R.L. Synchronization signal generation circuit and method
US5956289A (en) * 1997-06-17 1999-09-21 Micron Technology, Inc. Clock signal from an adjustable oscillator for an integrated circuit
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6115836A (en) * 1997-09-17 2000-09-05 Cypress Semiconductor Corporation Scan path circuitry for programming a variable clock pulse width
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US5923613A (en) * 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6111796A (en) * 1999-03-01 2000-08-29 Motorola, Inc. Programmable delay control for sense amplifiers in a memory
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7039822B2 (en) * 2003-02-27 2006-05-02 Promos Technologies Inc. Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US6944090B2 (en) * 2003-06-30 2005-09-13 International Business Machines Corporation Method and circuit for precise timing of signals in an embedded DRAM array
US7218161B2 (en) * 2004-08-20 2007-05-15 Macronix International Co., Ltd. Substantially temperature independent delay chain
US7103492B2 (en) * 2004-06-18 2006-09-05 Macronix International Co., Ltd. Process independent delay chain
US7830734B2 (en) 2008-03-14 2010-11-09 Promos Technologies Pte. Ltd. Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devices
US8254186B2 (en) * 2010-04-30 2012-08-28 Freescale Semiconductor, Inc. Circuit for verifying the write enable of a one time programmable memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4425633A (en) * 1980-10-06 1984-01-10 Mostek Corporation Variable delay circuit for emulating word line delay
US4687951A (en) * 1984-10-29 1987-08-18 Texas Instruments Incorporated Fuse link for varying chip operating parameters
JPH01256093A (ja) * 1988-04-05 1989-10-12 Matsushita Electric Ind Co Ltd レジスタファイル
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US4970418A (en) * 1989-09-26 1990-11-13 Apple Computer, Inc. Programmable memory state machine for providing variable clocking to a multimode memory
US5113373A (en) * 1990-08-06 1992-05-12 Advanced Micro Devices, Inc. Power control circuit
US5381379A (en) * 1992-12-03 1995-01-10 Sharp Kabushiki Kaisha Non-volatile dynamic random access memory device; a page store device and a page recall device used in the same; and a page store method and a page recall method
US5424985A (en) * 1993-06-30 1995-06-13 Sgs-Thomson Microelectronics, Inc. Compensating delay element for clock generation in a memory device

Also Published As

Publication number Publication date
US5663921A (en) 1997-09-02
JPH0896569A (ja) 1996-04-12
EP0668592A1 (de) 1995-08-23
EP0668592B1 (de) 2000-05-17
JP3011042B2 (ja) 2000-02-21
DE69424523T2 (de) 2001-01-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee