DE69431892D1 - Multiplexer - Google Patents

Multiplexer

Info

Publication number
DE69431892D1
DE69431892D1 DE69431892T DE69431892T DE69431892D1 DE 69431892 D1 DE69431892 D1 DE 69431892D1 DE 69431892 T DE69431892 T DE 69431892T DE 69431892 T DE69431892 T DE 69431892T DE 69431892 D1 DE69431892 D1 DE 69431892D1
Authority
DE
Germany
Prior art keywords
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69431892T
Other languages
English (en)
Other versions
DE69431892T2 (de
Inventor
Jerry D Moench
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Application granted granted Critical
Publication of DE69431892D1 publication Critical patent/DE69431892D1/de
Publication of DE69431892T2 publication Critical patent/DE69431892T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
DE69431892T 1993-03-01 1994-01-26 Multiplexer Expired - Fee Related DE69431892T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/024,521 US5307352A (en) 1993-03-01 1993-03-01 Switch matrix multiplexers

Publications (2)

Publication Number Publication Date
DE69431892D1 true DE69431892D1 (de) 2003-01-30
DE69431892T2 DE69431892T2 (de) 2003-11-13

Family

ID=21821020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69431892T Expired - Fee Related DE69431892T2 (de) 1993-03-01 1994-01-26 Multiplexer

Country Status (4)

Country Link
US (1) US5307352A (de)
EP (1) EP0614293B1 (de)
JP (1) JP3644982B2 (de)
DE (1) DE69431892T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563730B1 (en) 2002-04-09 2003-05-13 National Semiconductor Corporation Low power static RAM architecture
US6711051B1 (en) 2002-09-05 2004-03-23 National Semiconductor Corporation Static RAM architecture with bit line partitioning

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4390988A (en) * 1981-07-14 1983-06-28 Rockwell International Corporation Efficient means for implementing many-to-one multiplexing logic in CMOS/SOS
JPS58184822A (ja) * 1982-03-31 1983-10-28 Fujitsu Ltd 入力回路
JPS6030215A (ja) * 1983-07-28 1985-02-15 Toshiba Corp Ｃｍｏｓ論理回路
JPS61263313A (ja) * 1985-05-17 1986-11-21 Matsushita Electric Ind Co Ltd セレクタ付ラツチ回路
JPS62165788A (ja) * 1986-01-16 1987-07-22 Sharp Corp 半導体集積回路装置
US4868413A (en) * 1988-04-20 1989-09-19 International Business Machines Corporation Testable passgate logic circuits
US5001367A (en) * 1989-04-14 1991-03-19 Thunderbird Technologies, Inc. High speed complementary field effect transistor logic circuits
JPH0834395B2 (ja) * 1989-10-11 1996-03-29 株式会社東芝 スイッチ付き増幅回路
US5086427A (en) * 1990-04-09 1992-02-04 Unisys Corporation Clocked logic circuitry preventing double driving on shared data bus

Also Published As

Publication number Publication date
EP0614293B1 (de) 2002-12-18
EP0614293A3 (de) 1997-03-05
JPH06324775A (ja) 1994-11-25
EP0614293A2 (de) 1994-09-07
JP3644982B2 (ja) 2005-05-11
DE69431892T2 (de) 2003-11-13
US5307352A (en) 1994-04-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee