DE69504252T2 - Flache Grabenisolation mit dünner Nitridauskleidung - Google Patents

Flache Grabenisolation mit dünner Nitridauskleidung

Info

Publication number
DE69504252T2
DE69504252T2 DE69504252T DE69504252T DE69504252T2 DE 69504252 T2 DE69504252 T2 DE 69504252T2 DE 69504252 T DE69504252 T DE 69504252T DE 69504252 T DE69504252 T DE 69504252T DE 69504252 T2 DE69504252 T2 DE 69504252T2
Authority
DE
Germany
Prior art keywords
trench isolation
thin nitride
flat trench
nitride lining
lining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69504252T
Other languages
English (en)
Other versions
DE69504252D1 (de
Inventor
Paul Martin Fahey
Mutsuo Morikado
Erwin Hammerl
Herbert Lei Ho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69504252D1 publication Critical patent/DE69504252D1/de
Application granted granted Critical
Publication of DE69504252T2 publication Critical patent/DE69504252T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
DE69504252T 1994-06-29 1995-06-09 Flache Grabenisolation mit dünner Nitridauskleidung Expired - Lifetime DE69504252T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/268,378 US5447884A (en) 1994-06-29 1994-06-29 Shallow trench isolation with thin nitride liner

Publications (2)

Publication Number Publication Date
DE69504252D1 DE69504252D1 (de) 1998-10-01
DE69504252T2 true DE69504252T2 (de) 1999-04-22

Family

ID=23022734

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69504252T Expired - Lifetime DE69504252T2 (de) 1994-06-29 1995-06-09 Flache Grabenisolation mit dünner Nitridauskleidung

Country Status (4)

Country Link
US (1) US5447884A (de)
EP (1) EP0690493B1 (de)
JP (1) JP3079011B2 (de)
DE (1) DE69504252T2 (de)

Families Citing this family (142)

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DE69504252D1 (de) 1998-10-01
EP0690493B1 (de) 1998-08-26
EP0690493A3 (de) 1996-09-04
JP3079011B2 (ja) 2000-08-21
US5447884A (en) 1995-09-05
JPH0846029A (ja) 1996-02-16
EP0690493A2 (de) 1996-01-03

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