DE69522326D1 - Bitmap-orientierte adressierung für einen flash-speicher - Google Patents

Bitmap-orientierte adressierung für einen flash-speicher

Info

Publication number
DE69522326D1
DE69522326D1 DE69522326T DE69522326T DE69522326D1 DE 69522326 D1 DE69522326 D1 DE 69522326D1 DE 69522326 T DE69522326 T DE 69522326T DE 69522326 T DE69522326 T DE 69522326T DE 69522326 D1 DE69522326 D1 DE 69522326D1
Authority
DE
Germany
Prior art keywords
bitmap
flash memory
oriented addressing
addressing
oriented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69522326T
Other languages
English (en)
Other versions
DE69522326T2 (de
Inventor
Sherif Sweha
E Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69522326D1 publication Critical patent/DE69522326D1/de
Publication of DE69522326T2 publication Critical patent/DE69522326T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5631—Concurrent multilevel reading of more than one cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5632—Multilevel reading using successive approximation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
DE69522326T 1994-06-02 1995-05-17 Bitmap-orientierte adressierung für einen flash-speicher Expired - Fee Related DE69522326T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/253,902 US5497354A (en) 1994-06-02 1994-06-02 Bit map addressing schemes for flash memory
PCT/US1995/006308 WO1995034073A1 (en) 1994-06-02 1995-05-17 Bit map addressing schemes for flash memory

Publications (2)

Publication Number Publication Date
DE69522326D1 true DE69522326D1 (de) 2001-09-27
DE69522326T2 DE69522326T2 (de) 2002-06-13

Family

ID=22962167

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69522326T Expired - Fee Related DE69522326T2 (de) 1994-06-02 1995-05-17 Bitmap-orientierte adressierung für einen flash-speicher

Country Status (8)

Country Link
US (5) US5497354A (de)
EP (1) EP0763240B1 (de)
JP (1) JPH10501361A (de)
KR (1) KR100292661B1 (de)
CN (1) CN1101048C (de)
AU (1) AU2641395A (de)
DE (1) DE69522326T2 (de)
WO (1) WO1995034073A1 (de)

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US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
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US20030214867A1 (en) * 2002-05-17 2003-11-20 Matthew Goldman Serially sensing the output of multilevel cell arrays
US7324374B2 (en) * 2003-06-20 2008-01-29 Spansion Llc Memory with a core-based virtual ground and dynamic reference sensing scheme
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KR100822030B1 (ko) * 2006-12-26 2008-04-15 삼성전자주식회사 고 부호화율 부호를 이용한 멀티 레벨 셀 메모리 장치
US7743231B2 (en) * 2007-02-27 2010-06-22 International Business Machines Corporation Fast sparse list walker
US7577029B2 (en) 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
US7813167B2 (en) 2008-03-21 2010-10-12 Micron Technology, Inc. Memory cell
US7697325B2 (en) * 2007-09-24 2010-04-13 Sandisk Corporation Non-volatile memory cell endurance using data encoding
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US10013045B2 (en) 2011-12-21 2018-07-03 Intel Corporation Apparatus, method, and system for adaptive compensation of reverse temperature dependence
US9142321B2 (en) 2013-07-03 2015-09-22 Texas Instruments Incorporated Testing of non-volatile memory arrays
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KR20190130828A (ko) * 2018-05-15 2019-11-25 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템
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Also Published As

Publication number Publication date
US5815443A (en) 1998-09-29
DE69522326T2 (de) 2002-06-13
US5796667A (en) 1998-08-18
CN1101048C (zh) 2003-02-05
US6483742B1 (en) 2002-11-19
WO1995034073A1 (en) 1995-12-14
EP0763240B1 (de) 2001-08-22
CN1150492A (zh) 1997-05-21
AU2641395A (en) 1996-01-04
EP0763240A1 (de) 1997-03-19
KR100292661B1 (ko) 2001-06-15
JPH10501361A (ja) 1998-02-03
US5497354A (en) 1996-03-05
US5781472A (en) 1998-07-14
EP0763240A4 (de) 1998-08-19

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8339 Ceased/non-payment of the annual fee